Analog Devices AD9776 Instruction Manual page 42

AD9776/AD9778/AD9779
SYNC OUT DELAY
0x04 (0); 0x05 (7:4)
(~180ps/increment)
DACCLK
LVDS DAC
SYNC OUT (/1)
LVDS DAC
SYNC OUT (/4)
LVDS DAC
SYNC OUT (/16)
The sync output pulse must then be distributed from the master
to all the slave devices. This might require that the user imple-
ment circuitry outside of the device that splits the LVDS signal.
The splitter delivers the SYNC_O signal from the master to the
multiple slave device SYNC_I pins. A block diagram of this
implementation is shown in Figure 94. The equalization from
the CLK source and SYNC_O to the DACCLK and sync inputs
of the multiple AD977x devices is critical. For the multichip
synchronization to operate correctly at maximum specified
DAC sample rates, the DACCLK inputs must be phase aligned
to ±100 ps. The SYNC_I inputs must also be phase aligned to
±100 ps. At lower DAC sample rates, this timing alignment can
be relaxed.
LVDS DRIVER AND DELAY
EQUALIZATION
CLOCK
SOURCE
EQUALIZATION
Figure 94. Implementation of Sync Signal Distribution in Master/Slave Mode
SYNC TRIGGERING EDGE
0x07 (5)
1–RISING EDGE
0–FALLING EDGE
SYNC OUT DIVISOR IS CONTROLLED BY:
0x04 (3:1)
f
000 /32
DAC
f
001 /16
DAC
f
010 /8
DAC
f
011 /4
DAC
f
100 /2
DAC
f
101 /1
DAC
110 UNDEFINED
111 UNDEFINED
Figure 93. DACCLK/Sync Output Timing
SYNC OUT
SYNC IN
MASTER
DACCLK
DAC
SYNC IN
SLAVE
DACCLK
DAC
SYNC IN
SLAVE
DACCLK
DAC
CLOCK
SOURCE
EQUALIZATION
Figure 95. Implementation of Sync Signal Distribution in Slave Mode
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EQUALIZATION/FREQUENCY DIVISION
SYNC_IN
SLAVE
DACCLK
DAC
SYNC_IN
SLAVE
DACCLK
DAC
SYNC_IN
SLAVE
DACCLK
DAC