Analog Devices AD9776 Instruction Manual page 41

Dual, 12-/14-/16-bit, 1.0 gsps d/a converter
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The difference between the minimum delay shown in Figure 91
and the maximum delay shown in Figure 92 is the range
programmable via the DATACLK delay register. The delay
(in absolute time) when programming DATACLK delay
between 0000 and 1111 is a linear extrapolation between these
two figures. The typical delays per increment over temperature
are shown in Table 18.
Table 18. Data Delay Line Typical Delays Over Temperature
Delays
Delay Between Disabled and
Enabled
Average Delay per Increment
The frequency of DATACLK out depends on several program-
mable settings. Interpolation, zero stuffing, and interleaved/
dual port mode all have an effect on the DACCLK frequency.
The divisor function between DACCLK and DATACLK is equal
–40°C
+25°C
+85°C
370
416
432
171
183
197
Unit
ps
ps
Rev. 0 | Page 41 of 56
AD9776/AD9778/AD9779

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