Analog Devices AD9776 Instruction Manual page 34

AD9776/AD9778/AD9779
0.1μF
LVDS_P_IN
LVDS_N_IN
0.1μF
Figure 68. LVDS DACCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to DACCLK, as shown in Figure 68. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS to LVDS translator, then ac-coupled, as
described in this section. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 69.
0.1μF
TTL OR CMOS
CLK INPUT
Figure 69. TTL or CMOS DACCLK Drive Circuit
A simple bias network for generating VCM is shown in
Figure 70. It is important to use CVDD18 and CGND for the
clock bias circuit. Any noise or other signal that is coupled onto
the clock is multiplied by the DAC digital input signal and can
degrade the DAC's performance.
1kΩ
287Ω 0.1μF
Figure 70. DACCLK VCM Generator Circuit
Internal PLL Clock Multiplier/Clock Distribution
The internal clock structure on the devices allows the user to
drive the differential clock inputs with a clock at 1× or an
integer multiple of the input data rate or at the DAC output
sample rate. An internal PLL provides input clock multipli-
cation and provides all the internal clocks required for the
interpolation filters and data synchronization.
The internal clock architecture is shown in Figure 71. The
reference clock is the differential clock at Pins 5 and 6. This
clock input can be run differentially or singled-ended by
driving Pin 5 with a clock signal and biasing Pin 6 to the
midswing point of the signal at Pin 5. The clock architecture
can be run in the following configurations:
1. PLL Enabled (Reg. 0x09, Bit 7 = 1). The PLL enable switch
shown in Figure 71 is connected to the junction of the N1
dividers (PLL VCO divide ratio) and N2 dividers (PLL
loop divide ratio). Divider N3 determines the interpo-
CLK+
50Ω
V = 400mV
CM
50Ω
CLK–
50Ω
CLK+
CLK–
50Ω
BAV99ZXCT
HIGH SPEED
DUAL DIODE
V = 400mV
CM
V = 400mV
CM
CVDD18
1nF
1nF
CGND
lation rate of the DAC, and the ratio N3/N2 determines the
ratio of reference clock/input data rate. The VCO runs
optimally over the range of 1.0 GHz to 2.0 GHz, so that N1
keeps the speed of the VCO within this range, although the
DAC sample rate can be lower. The loop filter components
are entirely internal and no external compensation is
necessary.
2. PLL Disabled (Reg. 0x09, Bit 7 = 0). The PLL enable switch
shown in Figure 71 is connected to the reference clock
input. The differential reference clock input is the same as
the DAC output sample rate. N3 determines the
interpolation rate.
REFERENCE CLOCK
(Pins 5 and 6)
DETECTION
PLL ENABLE
Table 17. VCO Frequency Range vs. PLL Band Select Value
PLL Band
Select
111111 (63)
111110 (62)
111101 (61)
111100 (60)
111011 (59)
111010 58)
111001 (57)
111000 (56)
110111 (55)
110110 (54)
110101 (53)
110100 (52)
110011 (51)
110010 (50)
110001 (49)
110000 (48)
101111 (47)
101110 (46)
101101 (45)
101100 (44)
Rev. 0 | Page 34 of 56
ADC
0x0A (4:0)
0x08 (7:2)
LOOP FILTER
BANDWIDTH VCO RANGE
INTERNAL
PHASE
VCO
LOOP
FILTER
÷N ÷N
2 1
0x09 (4:3) 0x09 (6:5)
PLL LOOP PLL VCO
DIVIDE RATIO DIVIDE RATIO
÷N
DATACLK OUT (Pin 37)
3
0x01 (7:6)
0x09 (7)
INTERNAL DAC SAMPLE
RATE CLOCK
Figure 71. Internal Clock Architecture
Typical PLL Lock Ranges
VCO Frequency Range in MHz
Typ at 25°C Typ over Temp
f f f
LOW HIGH LOW
Auto Mode
2056 2170 2105
2002 2113 2048
1982 2093 2029
1964 2075 2010
1947 2057 1992
1927 2037 1971
1907 2016 1951
1894 2003 1936
1872 1981 1913
1852 1960 1892
1841 1948 1881
1816 1923 1855
1796 1903 1835
1789 1895 1828
1764 1871 1803
1746 1853 1784
1738 1842 1776
1714 1820 1752
1700 1804 1737
0x0A (7:5)
PLL CONTROL
VOLTAGE RANGE
DAC
INTERPOLATION
RATE
f
HIGH
2138
2081
2061
2043
2026
2006
1986
1972
1952
1931
1920
1895
1874
1867
1844
1826
1815
1794
1779