Analog Devices AD9776 Instruction Manual page 26

AD9776/AD9778/AD9779
Table 11. SPI Register Description
Register Name Hex
Comm Register 00
00
00
00
00
00
Digital Control 01
Register
01
01
02
02
02
02
02
02
02
Sync Control Register 03
03
03
04
04
04
05
05
05
Address
Decimal Name
7 SDIO Bidirectional
6 LSB/MSB First
5 Software Reset
4 Power-Down Mode
3 Auto Power-Down Enable
1 PLL Lock (Read Only)
7:6 Filter Interpolation Factor
5:2 Filter Modulation Mode
0 Zero Stuffing
7 Data Format
6 Dual/Interleaved Data Bus
Mode
5 Real Mode
3 Inverse Sinc Enable
2 DATACLK Invert
1 TxEnable Invert
0 Q First
7:6 Data Clock Delay Mode
5:4 Extra Data Clock Divide Ratio
3:0 Reserved
7:4 Data Clock Delay
3:1 Output Sync Pulse Divide
0 Sync Out Delay
7:4 Sync Out Delay
3:1 Input Sync Pulse Frequency
0 Sync Input Delay
Function
0: Use SDIO pin as input data only
1: Use SDIO as both input and output data
0: First bit of serial data is MSB of data byte
1: First bit of serial data is LSB of data byte
Bit must be written with a 1, then 0 to soft reset
SPI register map
0: All circuitry is active
1: Disable all digital and analog circuitry, only SPI
port is active
Controls auto power-down mode, see Power-
Down and Sleep Modes section
0: PLL is not locked
1: PLL is locked
00:1× interpolation
01:2× interpolation
10:4× interpolation
11:8× interpolation
See Table 19 for filter modes
0: Zero stuffing off
1: Zero stuffing on
0: Signed binary
1: Unsigned binary
0: Both input data ports receive data
1: Data port 1 only receives data
0: Enable Q path for signal processing
1: Disable Q path data (internal Q channel clocks
disabled, I and Q modulators disabled)
0: Inverse sinc filter disabled
1: Inverse sinc filter enabled
0: Output DATACLK same phase as internal
capture clock
1: Output DATACLK opposite phase as internal
capture clock
Inverts the function of TxEnable Pin 39, see
Interleaved Data Mode section
0: First byte of data is always I data at beginning
of transmit
1: First byte of data is always Q data at beginning
of transmit
00: Manual, no error correction
Data Clock Output Divider (see Table 22 for
Divider Ratio)
Sets delay of DACCLK in to DATACLK out
Sets frequency of Sync_O pulses
Sync Output Delay, Bit 4
Sync Output Delay, Bit <3:0>
Input Sync Pulse Frequency Divider, see the
Sync Pulse Receiver (Slave Devices) section
Sync Input Delay, Bit 4
Rev. 0 | Page 26 of 56
Default
0
0
0
0
0
00
0000
0
0
0
0
0
0
0
00
00
000
0000
000
0
000
0