Interpolation Filter Minimum And Maximum Bandwidth Specifications; Driving The Dacclk Input - Analog Devices AD9776 Instruction Manual

INTERPOLATION FILTER MINIMUM AND
MAXIMUM BANDWIDTH SPECIFICATIONS
The AD977x uses a novel interpolation filter architecture that
allows DAC IF frequencies to be generated anywhere in the
spectrum. Figure 65 shows the traditional choice of DAC IF
output bandwidth placement. Note that there are no possible
filter modes in which the carrier can be placed near 0.5 × f
1.5 × f , 2.5 × f , etc.
DATA DATA
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–4 –3 –2 –1
f
OUT
ASSUMING 8× INTERPOLATION
Figure 65. Traditional Bandwidth Options for TxDAC Output IF
The filter architecture not only allows the interpolation filter
pass bands to be centered in the middle of the input Nyquist
zones (as explained in this section), but also allows the
possibility of a 3 × f /8 modulation mode. With all of these
DAC
filter combinations, a carrier of given bandwidth can be placed
anywhere in the spectrum and fall into a possible pass band of
the interpolation filters. The possible bandwidths accessible
with the filter architecture are shown in Figure 66 and
Figure 67. Note that the shifted and nonshifted filter modes
are all accessible by programming the filter mode for the
particular interpolation rate.
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–4 –3 –2 –1
f
OUT
ASSUMING 8× INTERPOLATION
Figure 66. Nonshifted Bandwidths Accessible with the Filter Architecture
0 1 2 3
(× Input Data Rate),
0 1 2 3
(× Input Data Rate),
10
0
–10
–20
–30
–40
,
DATA
–50
–60
–70
–80
–4
Figure 67. Shifted Bandwidths Accessible with the Filter Architecture
With this filter architecture, a signal placed anywhere in the
spectrum is possible. However, the signal bandwidth is limited
by the input sample rate of the DAC and the specific placement
of the carrier in the spectrum. The bandwidth restriction
resulting from the combination of filter response and input
sample rate is often referred to as the synthesis bandwidth, since
4
this is the largest bandwidth that the DAC can synthesize.
The maximum bandwidth condition exists if the carrier is
placed directly in the center of one of the filter pass bands. In
this case, the total 0.1 dB bandwidth of the interpolation filters
is equal to 0.8 × f
width as a fraction of DAC output sample rate drops by a factor
of 2 for every doubling of interpolation rate. The minimum
bandwidth condition exists, for example, if a carrier is placed at
0.25 × f . In this situation, if the nonshifted filter response is
DATA
enabled, the high end of the filter response cuts off at 0.4 × f
thus limiting the high end of the signal bandwidth. If the shifted
filter response is enabled instead, then the low end of the filter
response cuts off at 0.1 × f
signal bandwidth. The minimum bandwidth specification that
applies for a carrier at 0.25 × f
minimum bandwidth behavior is repeated over the spectrum
for carriers placed at (±n ± 0.25) × f

DRIVING THE DACCLK INPUT

The DACCLK input requires a low jitter differential drive
signal. It is a PMOS input differential pair powered from the
1.8 V supply, therefore,
it is important to maintain the specified 400 mV input
common-mode voltage. Each input pin can safely swing from
200 mV p-p to 1 V p-p about the 400 mV common-mode
voltage. While these input levels are not directly LVDS-
4
compatible, DACCLK can be driven by an offset ac-coupled
LVDS signal, as shown in Figure 68.
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AD9776/AD9778/AD9779
–3 –2 –1 0 1
f
(× Input Data Rate),
OUT
ASSUMING 8× INTERPOLATION
. As Table 16 shows, the synthesis band-
DATA
, thus limiting the low end of the
DATA
is therefore 0.3 × f
DATA
, where n is any integer.
DATA
2 3 4
,
DATA
. The
DATA