Analog Devices AD9776 Instruction Manual page 40

AD9776/AD9778/AD9779
REFERENCE CLOCK
DATACLK OUT
1
For an in-depth description of how TxDAC timing specifications are specified, please read Analog Devices, application note AN748, "Set-up and Hold Measurements in
High Speed CMOS Input DACs."
Using Data Delay to Meet Timing Requirements
To meet strict timing requirements at input data rates of up to
250 MSPS, the AD977x has a fine timing feature. Fine timing
adjustments can be made by programming values into the data
clock delay register (Reg. 0x04, Bit <7:4>). This register can be
used to add delay between the DACCLK in and the DATACLK
out. Figure 90 shows the default delay present when DATACLK
delay is disabled. The disable function bit is found in Reg. 0x02,
Bit 4. Figure 91 shows the delay present when DATACLK delay
is enabled and set to 0000. Figure 92 indicates the delay when
DATACLK delay is enabled and set to 1111. Note that the set-up
and hold times specified for data to DATACLK are defined for
DATACLK delay disabled.
TEK RUN: 5.00GS/s SAMPLE
2
1
CH1 1.00VΩ CH2 500mVΩ
Figure 90. Delay from DACCLK to DATACLK with DATACLK Delay Disabled
REFERENCE CLOCK
t
D
DATACLK OUT
INPUT DATA
Figure 88. Timing Specifications, PLL Enabled, Reference Clock = 2× Input Sample Rate
t
D
INPUT DATA
t
= 3ns MIN
S
t
= 0.78ns MIN
H
t
= 5.0ns TYP
D
(DATACLK DELAY DISABLED)
Figure 89. Timing Specifications, PLL Disabled, 4× Interpolation
Δ: 4.48nS
@: 40.28nS
M2.00ns CH1 420mV
t t
S H
t
S
TEK RUN: 5.00GS/s
2
1
CH1 1.00VΩ
Figure 91. Delay from DACCLK to DATACLK Out with DATACLK Delay = 0000
TEK RUN: 5.00GS/s
2
1
CH1 1.00VΩ
Figure 92. Delay from DACCLK to DATACLK Out with DATACLK Delay = 1111
Rev. 0 | Page 40 of 56
1
t
H
SAMPLE
CH2 500mVΩ M2.00ns CH1
SAMPLE
CH2 500mVΩ M2.00ns CH1
Δ: 4.76nS
@: 35.52nS
420mV
Δ: 7.84nS
@: 32.44nS
420mV