Analog Devices AD9776 Instruction Manual page 35

PLL Band
Select
101011 (43)
101010 (42)
101001 (41)
101000 (40)
100111 (39)
100110 (38)
100101 (37)
100100 (36)
100011 (35)
100010 (34)
100001 (33)
100000 (32)
011111 (31)
011110 (30)
011101 (29)
011100 (28)
011011 (27)
011010 (26)
011001 (25)
011000 (24)
010111 (23)
010110 (22)
010101 (21)
010100 (20)
010011 (19)
010010 (18)
010001 (17)
010000 (16)
001111 (15)
001110 (14)
001101 (13)
001100 (12)
001011 (11)
001010 (10)
001001 (9)
001000 (8)
000111 (7)
000110 (6)
000101 (5)
000100 (4)
000011 (3)
000010 (2)
000001 (1)
000000 (0)
Figure m Typical PLL Band Select vs. Frequency at 25°C
Typical PLL Lock Ranges
VCO Frequency Range in MHz
Typ at 25°C Typ over Temp
f f f
LOW HIGH LOW
1689 1790 1726
1657 1757 1695
1641 1738 1679
1610 1707 1649
1597 1689 1635
1568 1661 1607
1553 1641 1592
1525 1613 1562
1511 1595 1548
1484 1570 1519
1470 1552 1506
1441 1525 1474
1429 1509 1463
1403 1485 1433
1390 1469 1422
1362 1443 1391
1352 1429 1380
1325 1405 1352
1314 1390 1340
1290 1368 1315
1276 1351 1302
1253 1331 1277
1239 1313 1264
1183 1255 1205
1204 1275 1227
1151 1221 1172
1171 1240 1193
1148 1218 1170
1137 1204 1159
1116 1184 1137
1106 1171 1127
1086 1152 1106
1075 1138 1095
1055 1119 1075
1045 1107 1065
1027 1090 1047
1016 1076 1034
998 1059 1016
987 1046 1005
960 1017 977
933 989 949
908 962 923
883 936 898
859 911 873
VCO Frequency Ranges
Because the PLL band covers greater than a 2× frequency range,
there can be two options for the PLL band select: one at the low
f
end of the range and one at the high end of the range. Under
HIGH
these conditions, the VCO phase noise is optimal when the user
1764
selects the band select value corresponding to the high end of
1734
the frequency range. Figure 72 shows how the VCO bandwidth
1714
and the optimal VCO frequency varies with the band select
1684
value.
1666
1639
PLL Loop Filter Bandwidth
1617
The loop filter bandwidth of the PLL is programmed via SPI
1592
Reg. 0x0A, Bits <4:0>. Changing these values switches
1572
capacitors on the internal loop filter. No external loop filter
1549
components are required. This loop filter has a pole at 0 (P1),
1528
and then a zero- (Z1) pole (P2) combination. Z1 and P2 occur
1504
within a decade of each other. The location of the zero pole is
1487
determined by Bit <4:0>. For a setting of 00000, the zero pole
1464
occurs near 10 MHz. By setting Bits <4:0> to 11111, the Z1/P2
1447
combination can be lowered to approximately 1 MHz. The
1423
relationship between Bits <4:0> and the position of the zero
1407
pole between 1 MHz and 10 MHz is linear. The internal compo-
1385
nents are not low tolerance, however, and can drift by as much
1369
as ±30%.
1350
1332
For optimal performance, the bandwidth adjustment
1313
(Reg. 0x0A, Bits <4:0>) should be set to 11111 for all
1295
operating modes with PLL enabled. The PLL bias settings
1240
(Reg. 0x09, Bits <2:0>) should be set to 111. The PLL control
1259
voltage (Reg. 0x0A, Bits <7:5>) is read back and is proportional
1207
to the dc voltage at the internal loop filter output. With the PLL
1224
bias settings given in this section, the readback from the PLL
1204
control voltage should typically be 010 or possibly 001 or 011.
1189
Anything outside of this range indicates that the PLL is not
1170
operating correctly.
1157
60
1138
56
1124
52
48
1106
44
1093
40
1076
36
32
1062
28
1046
24
1032
20
16
1004
12
976
8
950
4
0
925
899
Rev. 0 | Page 35 of 56
AD9776/AD9778/AD9779
F (MHz)
VCO