Interleaved Data Mode; Timing Information - Analog Devices AD9776 Instruction Manual

The auto power-down enable bit (Reg. 0x00, Bit 3) controls the
power-down function for the digital section of the devices. The
auto power-down function works in conjunction with the
TXENABLE pin (Pin 39) according to the following:
TXENABLE (Pin 39) =
0: autopower-down enable =
0: Flush data path with 0s
1: Flush data for multiple DACCLK cycles; then
automatically place the digital engine in power-down
state. DACs, reference, and SPI port are not affected.
or TXENABLE (Pin 39) =
1: Normal operation
If the TxEnable invert bit (Reg. 0x02, Bit 1) is set, the function
of this TXENABLE pin is inverted.

INTERLEAVED DATA MODE

The TxEnable bit is dual function. In dual port mode, it is
simply used to power down the digital section of the devices. In
interleaved mode, the IQ data stream is synchronized to
TxEnable. Therefore, to achieve IQ synchronization, TxEnable
should be held low until an I data word is present at the inputs
to Data Port 1. If a DATACLK rising edge occurs while
TxEnable is at a high logic level, IQ data becomes synchronized
to the DATACLK output. TxEnable can remain high and
the input IQ data remains synchronized. To be backwards-
compatible with previous DACs from ADI, such as the AD9777
and AD9786, the user can also toggle TxEnable once during
each data input cycle, thus continually updating the synchroni-
zation. If TxEnable is brought low and held low for multiple
DACCLK cycles, then the devices flush the data in the interpo-
lation filters, and shut down the digital engine after the filters
are flushed. The amount of DACCLK cycles it takes to go into
this power-down mode is then a function of the length of the
equivalent 2×, 4×, or 8× interpolation filter. The timing of
TxEnable, I/Q select, filter flush, and digital power-down are
shown in Figure 86.
REFERENCE CLOCK
t
D
DATACLK OUT
INPUT DATA
Figure 87. Timing Specifications, PLL Enabled, Reference Clock = 1× Input Sample Rate
INTERLEAVED
INPUT DATA
TxENABLE
TxENABLE CAN REMAIN
HIGH OR TOGGLE FOR
I/Q SYNCHRONIZATION
The TxEnable function can be inverted by changing the status
of Reg. 0x02, Bit 1. The other bit that controls IQ ordering is the
Q-first bit (Reg. 0x02, Bit 0). With the Q-first bit reset to the
default of 0, the IQ pairing that is latched is the I1Q1, I2Q2, etc.
With IQ first set to 1, the first I data is discarded and the pairing
is I2Q1, I3Q2, etc. Note that with IQ-first set, the I data is still
routed to the internal I channel, the Q data is routed to the
internal Q channel, and only the pairing changes.

TIMING INFORMATION

Figure 87 to Figure 89 show some of the various timing
possibilities when the PLL is enabled. The combination of the
settings of N2 and N3 means that the reference clock frequency
can be a multiple of the actual input data rate. Figure 87 to
Figure 89 show, respectively, what the timing looks like when
N2/N3 = 1 and 2.
In interleaved mode, set-up and hold times of DATACLK out to
data in are the same as those shown in Figure 87 to Figure 89. It
is recommended that any toggling of TxEnable occurs concur-
rently with the digital data input updating. In this way, timing
margins between DATACLK, TxEnable, and digital input data
are optimized.
Figure 89 shows the timing specifications when PLL is disabled.
The reference clock is at the DAC output sample rate. In the
example shown in Figure 89, if PLL is disabled, the interpola-
tion is 4×. The set-up and hold time for the input data are with
respect to the rising edge of DATACLK out. Note that if
Reg. 0x02, Bit 2 is set, DATACLK out is inverted so the latching
clock edge becomes DATACLK out falling edge.
t t
S H
Rev. 0 | Page 39 of 56
AD9776/AD9778/AD9779
I1 Q1 I2 Q2
FLUSHING
INTERPOLATION DOWN DIGITAL
FILTERS
Figure 86. TxEnable Function
1
POWER
SECTION