Analog Devices AD9776 Instruction Manual page 44

AD9776/AD9778/AD9779
LVDS DIFFERENTIAL
SYNC INPUT
SYNC_I Timing Restrictions
The AD977x can register timing errors for the SYNC_I signals.
The block diagram for this synchronization logic is shown in
Figure 94, which is very similar to the data input synchro-
nization circuit shown in Figure 95. The difference is that the
0x05 (0), 0x06 (7:4)
EDGE DETECTOR, DETECTS
ON ONE OUT OF EVERY
32 DACCLK EDGES
SYNC
INPUT
DELAY
PROGRAMMABLE
DACCLK
DELAY
(Internal
Delayed)
PROGRAMMABLE
DELAY
Figure 97. Simplified Internal Synchronization Logic
Rev. 0 | Page 44 of 56
D
Q
FF1
IRQ, 0x19 (6)
0x06 (3:0)
IRQ ENABLE, 0x19 (2)
D
FF2
Q
CLK
D
REGISTERED
FF3
Q
SYNC_I_int
CLK
circuit shown in Figure 95 uses the DACCLK to properly
register SYNC_I. The delay is programmable by Reg. 0x06, Bits
<3:0>. IRQ is registered in Reg. 0x19, Bit 6.