Analog Devices AD9776 Instruction Manual page 27

Register Name Hex
Sync Control Register 06
06
07
07
07
07
PLL Control 08
08
09
09
09
09
Misc Control 0A
0A
I DAC Control Register 0B
0C
0C
0C
0D
Aux DAC1 Control
Register
0E
0E
0E
0E
Address
Decimal Name
7:4 Sync Input Delay
3:0 Input Sync Pulse Timing Error
Tolerance
7 Sync Receiver Enable
6 Sync Driver Enable
5 Sync Triggering Edge
4:0 Sync_I to Input Data
Sampling Clock Offset
7:2 PLL Band Select
1:0 VCO AGC Gain Control
7 PLL Enable
6:5 PLL VCO Divide Ratio
4:3 PLL Loop Divide Ratio
2:0 PLL Bias Setting
7:5 PLL Control Voltage Range
4:0 PLL Loop Bandwidth
Adjustment
7:0 I DAC Gain Adjustment
7 I DAC Sleep
6 I DAC Power-Down
1:0 I DAC Gain Adjustment
7:0 Aux DAC1 Gain Adjustment
7 Aux DAC1 Sign
6 Aux DAC1 Current Direction
5 Aux DAC1 Power-Down
1:0 Aux DAC1 Gain Adjustment
Function
See Multi-DAC Synchronization section for
details on using these registers to synchronize
multiple DACs.
VCO frequency range vs. PLL band select value
(see Table 17)
Lower number (low gain) is generally better for
performance.
0: PLL off, DAC rate clock supplied by outside
source
1: PLL on, DAC rate clock synthesized internally
from external reference clock via PLL clock
multiplier
FVCO/f
DAC
00 × 1
01 × 2
10 × 4
11 × 8
f /f
DAC REF
00 × 2
01 × 4
10 × 8
11 × 16
Always set to 111
000 to 111, proportional to voltage at PLL loop
filter output, readback only
See PLL Loop Filter Bandwidth section for details
(7:0) LSB slice of 10-bit gain setting word
for I DAC
0: I DAC on
1: I DAC off
0: I DAC on
1: I DAC off
(9:8) MSB slice of 10-bit gain setting word
for I DAC
(7:0) LSB slice of 10-bit gain setting word for Aux
DAC1
0: Positive
1: Negative
0: Source
1: Sink
0: Aux DAC1 on
1: Aux DAC1 off
(9:8) MSB slice of 10 bit gain setting word for Aux
DAC1
Rev. 0 | Page 27 of 56
AD9776/AD9778/AD9779
Default
0
0
0
0
0
0
110011
11
0
111
11111001
0
0
01
00000000
0
0
00