Analog Devices AD9776 Instruction Manual page 43

Sync Pulse Receiver (Slave Devices)
The following description of SYNC_I on the slave devices also
applies to the SYNC_I on the master device. The timing for
SYNC_I on the master must match that of the slave devices.
The SYNC_I pulses, referred to in Figure 94 and shown in more
detail in Figure 96 are not restricted by their duty cycle. The
only restriction is that each sync pulse remains high for at least
one DACCLK cycle. However, the slave DAC receiving the sync
pulse must know the speed of the input sync pulse.
The ratio of DACCLK to the SYNC_I speed is determined by
the values of the input sync pulse frequency (Reg. 0x05,
Bits <3:1>), as shown in Table 22.
Table 22.
Reg. 0x05, Bits <3:1> Divider Ratio
000 DACCLK/32 (default)
001 DACCLK/16
010 DACCLK/8
011 DACCLK/4
100 DACCLK/2
101 Undefined
110 Undefined
111 Undefined
SYNC_I_int (Post SYNC DELAY)
SYNC_I_int (Post SYNC DELAY)
SYNC_stripped (Post Edge Detector)
SYNC INPUT DELAY
0x06 (7:4)
(~100ps/increment)
DATA CLOCK OFFSET
(1 DACCLK cycle/increment)
DACCLK_ext
DACCLK_int
(Prop, Delay)
SYNC_I_ext_min_dutycycle
SYNC_I_ext_50%dutycycle
DCLK_SMP
DCLK_OUT
0x07 (4:0)
Figure 96. Internal and External Timing for Master or Slave Device
Internal Synchronization in Slave Devices
The internal timing functions in the slave device are shown in
Figure 96. The duty cycle of the SYNC_I signal is not restricted
to 50%. The minimum restriction on duty cycle for SYNC_I is
that it stays high for at least one full DACCLK cycle. Figure 96
shows two possible SYNC_I signals: one with a 50% duty cycle
and another one with a minimum duty cycle. More details on
SYNC_I timing restriction are given in the SYNC_I Timing
Restrictions section.
DACCLK samples SYNC_I and generates the internal sync signal
(SYNC_I_int). The period of SYNC_I_int is always DACCLK/32.
If the rate of SYNC_I is greater than DACCLK/32, the extra
pulses are stripped off. Figure 96 shows that the SYNC_I period
= DACCLK/16, so that every other SYNC_I pulse is stripped.
DACCLK_SMP is an internal signal, equal in frequency to the
DACCLK/interpolation rate. DACCLK_SMP is synthesized by
DACCLK, but synchronized by SYNC_I. Note that there is also
a programmable delay (sync input delay) between SYNC_I_int
and DACCLK_SMP. This programmable delay adds even more
flexibility to the timing interface. Figure 96 shows that the
interpolation is set to 8× (DACCLK_SMP rate is 1/8 that of
DACCLK).
DATA CLOCK DELAY
0x04 (7:4)
Rev. 0 | Page 43 of 56
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