Spi Register Map; Changes To Table 13 - Analog Devices AD9776A Manual

AD9776A/AD9778A/AD9779A

SPI REGISTER MAP

Note that all unused register bits should be kept at the device default values.
Table 13.
Address
Register
Hex Decimal
Name
Comm 0x00 00
Digital 0x01 01
Control
0x02 02
Sync 0x03 03
Control
0x04 04
0x05 05
0x06 06
0x07 07
PLL 0x08 08
Control
0x09 09
Misc. 0x0A 10
Control
I DAC 0x0B 11
Control
0x0C 12
AUX 0x0D 13
DAC1
0x0E 14
Control
Q DAC 0x0F 15
Control
0x10 16
AUX 0x11 17
DAC2
0x12 18
Control
0x13 19 to 24
to
0x18
Interrupt 0x19 25
Version 0x1F 31
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Bit 7 Bit 6 Bit 5
SDIO LSB/MSB Software
Bidirectional First Reset
Interpolation Factor<1:0>
Data Format Interleaved Real Mode
Data Bus
DATACLK Reserved DATACLK Divide<1:0>
Delay Mode (Set to 1)
DATACLK Delay<3:0>
SYNC_O Delay<3:0>
SYNC_I Delay<3:0>
SYNC_I SYNC_O SYNC_O
Enable Enable Triggering
Edge
PLL Band Select<5:0>
PLL Enable PLL VCO Divide
Ratio<1:0>
VCO Control Voltage<2:0> (Read Only)
I DAC Sleep I DAC
Power-
Down
Auxiliary Auxiliary Auxiliary
DAC1 Sign DAC1 DAC1
Current Power-
Direction Down
Q DAC Q DAC
Sleep Power-
Down
Auxiliary Auxiliary Auxiliary
DAC2 Sign DAC2 DAC2
Current Power-
Direction Down
Data Timing Sync Timing
Error IRQ Error IRQ
Rev. A | Page 26 of 60
Bit 4 Bit 3 Bit 2
Power- Auto
Down Power-
Mode Down
Enable
Filter Modulation Mode<3:0>
DATACLK Inverse DATACLK
Delay Sinc Invert
Enable Enable
Data Timing Margin<3:0>
SYNC_O Divide<2:0>
SYNC_I Ratio<2:0>
SYNC_I Timing Margin<3:0>
Clock State<4:0>
PLL Loop Divide
Ratio<1:0>
PLL Loop Bandwidth<4:0>
I DAC Gain Adjustment<7:0>
Auxiliary DAC1 Data<7:0>
Q DAC Gain Adjustment<7:0>
Auxiliary DAC2 Data<7:0>
Reserved
Data Data Sync
Timing Timing Timing
Error Error Error IRQ
Type IRQ Enable
Enable
Version<7:0>
Bit 1 Bit 0 Def.
PLL Lock 0x00
Indicator
(Read
Only)
DATACLK Zero 0x00
Delay<4> Stuffing
Enable
TxEnable Q First 0x00
Invert
0x00
SYNC_O 0x00
Delay<4>
SYNC_I 0x00
Delay<4>
0x00
0x00
PLL VCO Drive<1:0> 0xE7
PLL Bias<2:0> 0x52
0x1F
0xF9
I DAC Gain 0x01
Adjustment<9:8>
0x00
Auxiliary DAC1 0x00
Data<9:8>
0xF9
Q DAC Gain 0x01
Adjustment<9:8>
0x00
Auxiliary DAC2 0x00
Data<9:8>
Internal 0x00
Sync
Loopback
0x03