Spi Register Map - Analog Devices AD9779 Preliminary Technical Data

AD9779

SPI Register Map

Register Address
Name
Comm 00h 00 SDIO
Register Bidirectional
Digital 01h 01 Filter Interpolation Factor
<1: 0>
Control
Register
02h 02 Data Format
Sync 03h 03 Data Delay Mode <1:0>
Control
04h 04 Sync Out Delay <3:0>
05h 05 Sync Enable
Interrupt 06h 06 Data Delay
Register IRQ
07h 07 PLL Band Select <4:0>
PLL Control
08h 08 PLL Enable
09h 24 PLL Error
Misc.
Control Source
Register
I DAC 0Ah 09 IDAC Gain Adjustment <7:0>
Control
Register
0Bh 10 IDAC SLEEP
Aux 1 DAC 0Ch 11 Auxiliary DAC1 Data <7:0>
Control
Register
0Dh 12 Auxiliary
DAC1 Sign
Q DAC 0Eh 13 QDAC Gain Adjustment <7;0>
Control
Register
0Fh 14 QDAC SLEEP
Bit 7 Bit 6
LSB,MSB First Software
Reset
Filter Interpolation Mode <4:0>
One Port Real Mode
Mode
Data Clock Delay <2:0>
Sync Driver Dac Clock Offset <2:0>
Enable
Sync Delay Cross
IRQ Control IRQ
PLL Output Freq Divide
<1:0>
PLL Ref PLL Gain <2:0>
Bypass
IDAC Power
Down
Auxiliary Auxiliary
DAC1 DAC1 Sleep
Current
Direction
QDAC Sleep
Bit 5 Bit 4 Bit 3
Power Auto
Down Power
Mode Down
Enable
Inverse
Sinc
Enable
Sync Window Delay <3:0>
Data Delay
IRQ Enable
PLL Loop Freq Divide
<1:0>
Rev. PrD | Page 14 of 34
Preliminary Technical Data
Bit 2 Bit 1
PLL Lock
Indicator
Zero
Stuffing
Enable
DATACLK IQ Select Q First
Invert Invert
Data Window Delay <2:0>
Sync Delay Cross
IRQ Enable Control IRQ
Enable
PLL Loop Cap Select <2:0>
PLL Loop Filter Pole/Zero <2:0>
PLL Bias <2:0>
IDAC Gain Adjustment
<9:8>
Auxiliary DAC1 Data
<9:8>
QDAC Gain Adjustment
<9:8>
Bit 0 Default
00h
00h
00h
00h
00h
00h
00h
CFh
37h
38h
F9h
01h
00h
00h
F9h
01h