Signal Description; Qspi Flash Programming Via Jtag; Slave Serial Configuration - Signals Description - Enclustra Mars AX3 User Manual

3.6.1

Signal Description

Signal Name
FLASH_CLK_FPGA_CCLK
FLASH_DO_FPGA_DIN
FPGA_INIT#
FPGA_DONE
FPGA_PROG#
FPGA_MODE
Table 30: Slave Serial Configuration - Signals Description
Warning!
Note that after the rising edge of FPGA_DONE, the FPGA still requires a number of clock cycles to finish
the configuration. Therefore, if the FPGA_CCLK and FPGA_DIN pins are used in the FPGA design, the
user must ensure that these are tri-stated by the FPGA logic for the appropriate amount of time. Details
on the configuration time are available in Xilinx AR #42128.
3.7

QSPI Flash Programming via JTAG

Enclustra MCT [15] can be used to program the QSPI flash equipped on any Mars AX3 FPGA module revision
as an alternative to programming via JTAG.
To use quad-mode for the SPI flash, the bitstream generation option "SPI_buswidth" must be set to 4 in the
Xilinx tools. In addition, the SPI flash must be configured to 4-bit mode when programming the flash.
Please note that the FPGA_MODE pin must be pulled low for a successful flash programming using Xilinx
iMPACT. Otherwise, iMPACT will report an error, as it tries to configure the FPGA from the flash after pro-
gramming.
Modules Revisions 1 and 2
Please note that Xilinx iMPACT has limited support on the Artix-7 family and on the Winbond flash equipped
on revision 1 and 2 modules.
The QSPI Flash on the MA-AX3-100 module can be programmed with the Xilinx iMPACT tool via JTAG. The
128 Mbit Winbond flash device W25Q128FV is not supported by all versions of iMPACT; in some versions
the flash programming only works if the "W25Q128BV" is selected.
There is currently no Xilinx tool to configure the QSPI Flash on the MA-AX3-50 and MA-AX3-35 modules
from revisions 1 and 2. This is because the Xilinx iMPACT tool does not have support for the equipped Artix-7
devices and Vivado has no support for the W25Q128FV flash.
Modules Revision 3 and newer
Modules revision 3 and newer are equipped with Cypress (Spansion) QSPI flash, which is supported by the
Vivado and SDK tools. For more information, please refer to the Xilinx Documentation [20].
D-0000-426-004
Description
Configuration clock
Configuration data
Is pulled low by the FPGA if any CRC error occurs during the configuration; it
may be used as an input to delay the start of the FPGA configuration.
Goes high after a successful FPGA configuration
When pulled low, the FPGA configuration sequence is cleared and all pins are
tri-stated. The rising edge of FPGA_PROG# initializes the configuration.
Must be pulled high or left open during configuration
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