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Enclustra Mars AX3 User Manual

Fpga module
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Mars AX3 FPGA Module
Reference Design for Mars PM3 Base Board
Purpose
The purpose of this document is to present to the user the overall view of the Mars AX3 FPGA module
reference design and to provide the user with a step-by-step guide to the complete Xilinx® FPGA design
flow used for the Mars AX3 FPGA module.
Summary
This document first gives an overview of the Mars AX3 FPGA module reference design and then guides
through the complete Xilinx FPGA design flow for the Mars AX3 FPGA module in the getting started
section. In addition, the internals and the boot options of the Mars AX3 FPGA module reference design
are described.
Product Information
Product
Document Information
Reference / Version / Date
Approval Information
Written by
Verified by
Approved by
User Manual
Code
MA-AX3
Reference
D-0000-492-002
Name
DDUE/ARUD/ESOM
GKOE
IJOS
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Name
Mars AX3 FPGA Module
Version
2022.1_v1.0.2
Position
Design Engineer
Design Expert
Manager, BU SP
Phone +41 43 343 39 43 – www.enclustra.com
Date
04.01.2023
Date
30.09.2022
05.10.2022
15.10.2022

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Summary of Contents for Enclustra Mars AX3

  • Page 1 User Manual Purpose The purpose of this document is to present to the user the overall view of the Mars AX3 FPGA module reference design and to provide the user with a step-by-step guide to the complete Xilinx® FPGA design flow used for the Mars AX3 FPGA module.
  • Page 2 License Copyright 2023 by Enclustra GmbH, Switzerland. Permission is hereby granted, free of charge, to any person obtaining a copy of this hardware, software, firmware, and associated documentation files (the ”Product”), to deal in the Product without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or...

  • Page 3: Table Of Contents

    Table of Contents Overview Introduction ..........Prerequisites .

  • Page 4: Overview

    A Xilinx JTAG programmer (e.g. Platform Cable USB II) (optional May be used for flash programming, for FPGA device configuration or for FTDI configuration. Any FTDI device present on Enclustra hardware can be configured to Xilinx JTAG mode using the Enclustra MCT software [5]. D-0000-492-002 4 / 24 Version 2022.1_v1.0.2, 04.01.2023...

  • Page 5: Reference Design Description

    2 Reference Design Description Enclustra Mars PM3 Base Board Enclustra Mars AX3 FPGA Module Xilinx Artix-7 FPGA Microblaze system Local Memory Microblaze CPU User EEPROM QSPI EEPROM Flash Controller Controller DDR3(L) SDRAM System SDRAM Controller Monitor FTDI USB Micro USB...

  • Page 6: Gpios

    Table 2: FPGA Firmware I/O Configuration 2.1.5 For available devices on the I2C bus refer to the Mars AX3 FPGA Module and Mars PM3 Base Board User Manual [3] [4]. An I2C Application Note is available as well providing sample code and more details about using I2C on Enclustra hardware [8].

  • Page 7: Ethernet

    An Ethernet Application Note is available as well providing sample code and more details about using the Ethernet on Enclustra hardware [9]. Please note that the RGMII delays in the Ethernet PHY need to be configured according to the Mars AX3 FPGA module User Manual [3] when the Ethernet interface can be used.

  • Page 8: Getting Started

    Essential Information Warning! Always check that the Mars AX3 FPGA module is aligned to the socket of the Mars PM3 base board accordingly. The base board and module may be damaged if the module is not inserted properly and powered up.

  • Page 9: Hardware Setup

    Make sure the SD card slot of the Mars PM3 base board is empty (see label SD Card in Figure Mount the Mars AX3 FPGA module to the Mars PM3 base board. Connect the micro USB cable between your computer and the Mars PM3 base board. Use the micro USB port labeled USBUB in Figure 2.

  • Page 10: Fpga Bitstream Generation

    Tcl file. 2. Save the file after editing. Start Xilinx Vivado 2022.1 and create the Mars AX3 FPGA module reference design project: 1. Click on the Tcl console at the bottom of the page and type: (a) cd {<base_dir>}...

  • Page 11: Vitis Workspace Preparation

    Step Description Export the hardware system information (required for the Vitis IDE): 1. File Export Export Hardware and click Next 2. Select Include Bitstream and click Next 3. Leave the file name and export location as default and click Next 4.

  • Page 12: Vitis Workspace Preparation Step-By-Step Guide

    Step Description Create a new application 1. File Application Project 2. In the New Application Project window: (a) Click ”Next” on the Welcome page (if you have not disabled it) (b) Select the previously generated hardware platform and click ”Next” (c) For Project Name type a description for the new application e.g.

  • Page 13: Running Software Applications

    Running Software Applications This section describes how to run software applications on the Mars AX3 FPGA module. The steps are generic, and apply to the software example templates in the Vitis IDE. Step Description Create a run configuration for the application in Vitis IDE 2022.1: 1.

  • Page 14: Run Configurations Settings - Application Tab

    Figure 3: Run Configurations Settings - Application Tab Figure 4: Run Configurations Settings - Target Setup Tab D-0000-492-002 14 / 24 Version 2022.1_v1.0.2, 04.01.2023...

  • Page 15: Boot Configurations

    You need to select the file corresponding to the Mars AX3 FPGA module variant. Pre-generated binaries for any AX3 variant are released on the AX3 Reference Design Github page.

  • Page 16: Generate Linker Scripts Settings

    Step Description It has been found that in Vivado the download.bit image file can be written to the QSPI flash by renaming it to download.bin. If the system should not boot or work as expected afterwards, a .bin or .mcs file can be generated as in the Vivado GUI: 1.

  • Page 17: Qspi Flash Boot

    Figure 6: Initialize Block RAM settings QSPI Flash Boot 4.1.1 Preparing the Hardware Step Description Remove the power supply from the Mars PM3 base board (see label 12 V DC in Figure 2). Enable the QSPI flash boot mode by setting the configuration DIP switches on the Mars PM3 base board as follows (see labels CFG A CFG B...
  • Page 18 Add Configuration Mem- ory Device (see Figure 8) (a) For Select Configuration Memory Part choose the memory part according to the Mars AX3 FPGA Module User Manual [3], part type single. This is in most cases s25fl512s-spi-x1_x2_x4. (b) Hit OK 4.

  • Page 19: Qspi Flash Programming Settings In Vitis

    Step Description Optional - alternatively, Enclustra Module Configuration Tool (MCT) [5] can be used to pro- gram the QSPI flash. Note that the .mcs format is not supported. Close all other tools that may be connected to the FTDI device (Vivado Hardware Manager, Vitis, UART terminal).

  • Page 20: Qspi Flash Programming Settings In Vivado - Adding The Memory Device

    Figure 8: QSPI Flash Programming Settings in Vivado - Adding the Memory Device Figure 9: QSPI Flash Programming Settings in Vivado Warning! Some Vivado and Vitis tool versions are reporting problems when configuring certain FPGA devices or when using particular boot modes. Please try different tool versions and check the Xilinx documenta- tion and forums for help on the reported issue.

  • Page 21: Booting From The Qspi Flash

    4.1.3 Booting from the QSPI Flash Step Description Check that the hardware configuration is done according to Section 4.1.1. Press the power-on reset button (see label in Figure 2) and release it after a second. Table 11: Booting from the QSPI Flash Step-by-Step Guide D-0000-492-002 21 / 24 Version 2022.1_v1.0.2, 04.01.2023...

  • Page 22: Troubleshooting

    2. If built-in JTAG is used, check that the FTDI device is configured to Xilinx JTAG mode. This can be done using the Enclustra MCT software [5]. More information on the Xilinx JTAG mode configuration on the Mars PM3 base board can be retrieved from the Mars PM3 base board user manual [4].

  • Page 23: Qspi Boot Issues

    2. Check that the baud rate for the UART in the block design matches the baud rate set in the terminal program 3. Make sure that Enclustra MCT software is not open. After closing it, unplug and plug in again the USB cable corresponding to the UART communication.
  • Page 24 [1] Vivado Design Suite User Guide, Embedded Processor Hardware Design, UG898, Xilinx, 2020 [2] Vivado Design Suite Tutorial Embedded Processor Hardware Design, UG940, Xilinx, 2020 [3] Mars AX3 FPGA Module User Manual Ask Enclustra for details [4] Mars PM3 Base Board User Manual...

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