Sdram Memory; Flag Pins - Analog Devices ADSP-21161N EZ-KIT Lite Manual

SDRAM Memory

The SDRAM memory connects to the SDRAM controller of the proces-
sor. A set of programmable timing parameters is available to configure the
SDRAM banks to support slower memory accesses. Care must be taken
when configuring the SDRAM control registers. For more information
regarding the setup of the SDRAM controller, please refer to the
ADSP-21161 SHARC Processor Hardware Reference. An example program
is included in the EZ-KIT Lite installation directory to demonstrate the
SDRAM setup.
When you are in a VisualDSP++ session connected to the ADSP-21161N
EZ-KIT Lite board, the SDRAM registers are configured automatically
through the debugger each time the processor is reset. Clearing the Auto
configure external memory check box on the Target Options dialog box,
which is accessible through the Settings pull-down menu, disables this
feature. For more information see the online Help.

Flag Pins

The ADSP-21161N processor holds twelve asynchronous flag IO pins.
Ten of these pins (
program.
After the processor is reset, the flags are configured as inputs. The direc-
tions of the flags are configured though the
read though the
Table 1-2. For more information on flags, refer to the ADSP-21161
SHARC Processor Hardware Reference.
ADSP-21161N EZ-KIT Lite Evaluation System Manual
www.BDTIC.com/ADI
) are available for interaction with the running
FLAG0–9
registers. The
FLAGS
Using ADSP-21161N EZ-KIT Lite
register and are set and
MODE2
registers are summarized in
FLAGS
1-9