Clock Mode Jumpers (Jp21); Table 4-7: Boot Mode Select Jumper (Jp20) Settings; Table 4-8: Clock Mode Selections - Analog Devices ADSP-21161N EZ-KIT LITE Manual

Table 4-7: Boot Mode Select Jumper (JP20) Settings

EBOOT
Pins 1 & 2
Not
Installed
Installed
Installed
Installed
Installed
Not
Installed

4.3.12 Clock Mode Jumpers (JP21)

JP21 controls the speed for the core and external port of the ADSP-21161N. The
frequency supplied to CLKIN of the DSP may be changed by removing the 12.5
MHz oscillator (U24) that is shipped with the board and replacing it with a
different oscillator or crystal (Y2). A clock mode and frequency should be
selected so that the min and max specs of the ADSP-21161N are not exceeded.
For more information on clock modes, see the ADSP-21161N DSP Hardware
Reference. Table 4-8

Table 4-8: Clock Mode Selections

CLKDBL
Pins 1 & 2
Not
Installed
Not
Installed
Not
Installed
Installed
Installed
Installed
ADSP-21161N EZ-KIT Lite Evaluation System Manual
LBOOT BMS
Pins 3 & 4 Pins 5 & 6
Not
Installed Installed
(Output)
Not
Installed Installed
(Input)
Not Installed
Installed (Input)
Not
Not
Installed
Installed
(Input)
Installed
Installed
(Input)
Not Installed
Installed (Input)
shows the jumper setting for the clock modes.
CLK_CFG1 CLK_CFG0
Pins 3 & 4 Pins 5 & 6
Installed Installed
Installed Not Installed
Not Installed Installed
Installed Installed
Installed Not Installed
Not Installed
Installed
Boot Mode
EPROM BOOT(DEFAULT)
Host Processor Boot
Serial Boot via SPI
Link Port Boot
No Boot
Reserved
Core Clock EP Clock
Ratio Ratio
2:1 1x
3:1 1x
4:1 1x
4:1 2x
6:1 2x
8:1 2x (Default)
4-9