Renesas R-IN32M3 Series User Manual page 29

R-IN32M3-CL User's Manual
2.1.13 CC-Link IE Field Pins (Intelligent Device Station)
Pin Name
CCI_RUNLEDZ
CCI_DLINKLEDZ
CCI_ERRLEDZ
CCI_LERR1LEDZ
CCI_LERR2LEDZ
CCI_SDLEDZ
CCI_RDLEDZ
CCI_NMIZ
CCI_WDTIZ
Note
CCI_WAITEDGEH
Note
CCI_WRLENH
CCI_PHYREZ1
CCI_PHYREZ0
CCI_INTZ
CCI_CLK2_097M
Note:
When user does boot with the external memory boot mode, external serial flash ROM boot mode,
or instruction RAM boot mode, be sure not to input the low level to P33 (multiplexed with
CCI_WAITEDGEH) and P34 (multiplexed with CCI_WRLENH) pins during a reset. P33 and P34 pins
should be left open circuit or the high level should be input to the pins during a reset.
If you input the low level to P33 and P34 pins during a reset, you cannot access the CC-Link IE
field from the CPU and DMA controller of the R-IN32M3.
R18UZ0005EJ0400
Dec. 28, 2018
I/O Function
O Run status output
O Cyclic communication status output
O Field network error status output
O Link error status output 1
O Link error status output 2
O Transmission state output
O Port reception state output
O Output NMI interrupt to MCU
I Input from external watchdog timer
I/O Wait synchronized edge setting
0: Fall edge mode
1: Rise edge mode
I/O WRL signal enable setting
0: Write byte enable operation
1: Normal byte enable operation
O PHY reset output 1
O PHY reset output 0
O Output interrupt to MCU
I 2.097152-MHz clock
(crystal oscillator)
Shared Level during & after
Port Active
P00 Low Hi-Z (High)
P02 Low
P03 Low
P04 Low
P05 Low
P06 Low
P07 Low
P12 Low Hi-Z (High)
P13 Low
P33 -
P34 -
P56 Low
P57 Low
P66 Low
- - -
2. Pin Functions
Reset
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