Renesas R-IN32M3 Series User Manual page 9

Figure 3.1 Memory Map (All) .............................................................................................................................. 41
Figure 3.2 Memory Map (APB Peripheral Registers Area) ................................................................................. 42
Figure 3.3 Memory Map (External Memory Area) .............................................................................................. 43
Figure 3.4 Memory Map (CC-Link Master Area) ................................................................................................ 43
Figure 3.5 External MCU Interface Area ............................................................................................................. 44
Figure 6.1 Timing of Data Sampling and Period of Waiting for the Bus of a CC-Link IE Field Network .......... 54
Figure 6.2 Procedure for Switching Access Path to the CC-Link IE Field .......................................................... 56
Figure 7.1 Basic Circuit Configuration of Ports ................................................................................................... 59
Figure 7.2 Port Registers (in 8-Bit Notation) ....................................................................................................... 66
Figure 7.3 Port Registers (in 16-Bit Notation) ..................................................................................................... 67
Figure 7.4 Port Registers (in 32-Bit Notation) ..................................................................................................... 68
Figure 7.5 Port Mode Registers (in 8-Bit Notation) ............................................................................................. 69
Figure 7.6 Port Mode Registers (in 16-Bit Notation) ........................................................................................... 70
Figure 7.7 Port Mode Registers (in 32-Bit Notation) ........................................................................................... 71
Figure 7.8 Port Mode Control Registers (in 8-Bit Notation) ................................................................................ 72
Figure 7.9 Port Mode Control Registers (in 16-Bit Notation) .............................................................................. 73
Figure 7.10 Port Mode Control Registers (in 32-Bit Notation) .............................................................................. 75
Figure 7.11 Port Function Control Registers (in 8-Bit Notation) ........................................................................... 76
Figure 7.12 Port Function Control Registers (in 16-Bit Notation) ......................................................................... 77
Figure 7.13 Port Function Control Registers (in 32-Bit Notation) ......................................................................... 78
Figure 7.14 Port Function Control Expansion Registers (in 8-Bit Notation) ......................................................... 79
Figure 7.15 Port Function Control Expansion Registers (in 16-Bit Notation) ....................................................... 80
Figure 7.16 Port Function Control Expansion Registers (in 32-Bit Notation) ....................................................... 81
Figure 7.17 Port Pin Input Registers (in 8-Bit Notation) ....................................................................................... 82
Figure 7.18 Port Pin Input Registers (in 16-Bit Notation) ..................................................................................... 83
Figure 7.19 Port Pin Input Registers (in 32-Bit Notation) ..................................................................................... 84
Figure 7.20 Configuration of Trigger-Synchronous Ports .................................................................................... 103
Contents of Figures
Contents-4