Renesas R-IN32M3 Series User Manual page 55

R-IN32M3-CL User's Manual
4. Exception Handling
The R-IN32M3 uses the interrupt controller of Cortex-M3.
Refer to the following URL of Arm for the exceptions handling operation of Cortex-M3.
http://infocenter.arm.com/help/topic/com.arm.doc.set.cortexm/index.html
4.1 Exceptions List
Exception numbers 1 to 15 are system exceptions of the Cortex-M3 CPU. Interrupts from the internal hardware of the
R-IN32M3 and external pins are assigned to exception number 16 and higher exception numbers.
Exception
No. Exception Type
1 Reset
2 NMI
3 Hard fault
4 Memory manage fault
5 Bus fault
6 Use fault
7 to 10 Reserved
11 SVCall
12 Debug monitor
13 Reserved
14 PendSV
15 SysTick
16 and R-IN32M3 specific Interrupt
higher
R18UZ0005EJ0400
Dec. 28, 2018
Priority
-3 - Input on the reset pin (RESETZ, PONRZ, or
(highest) HOTRESETZ)
- Reset by the watchdog timer
- Set the SYSRESETREQ bit in NVIC of the Cortex-M3
CPU to 1
- Reset by the SYSRESET register
-2 - Input on the NMI pin
- Generation of NMI by the watchdog timer
-1 All classes of exceptions that no other exception handler
can handle.
Used to call up a response to a fault.
Programmable Exception from the MPU
Programmable Bus error in access through the bus to the area outside the
scope of management by the MPU
Programmable Error in instruction execution, including the execution of an
undefined instruction
- -
Programmable System service call by an SVC instruction
Programmable Debug monitor
- -
Programmable Request for system service that can be kept pending
Programmable Indication from the system timer
Programmable Interrupt from the internal hardware of the R-IN32M3 and
external pins
4. Exception Handling
Remark
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