Renesas R-IN32M3 Series User Manual page 12

R-IN32M3-CL User's Manual
1.2 Overview
Table 1.1 Overview of R-IN32M3-CL
Item
CPU cores
Operating frequency
Instruction set
Instruction RAM
Data RAM
Buffer RAM
Internal system bus
DMA bus (system bus side)
Boot options
External memory support
External MCU interface
Serial flash ROM memory controller
Interrupt
Internal peripheral circuit
I/O ports
Timers (three systems)
R18UZ0005EJ0400
Dec. 28, 2018
Product
Arm Cortex-M3 32-bit RISC CPU
+ Real-Time OS Accelerator (Hardware Real-Time OS, HW-RTOS)
100 MHz
®
Thumb -2 instruction Arm v7-M
768 Kbytes (RAM with ECC)
512 Kbytes (RAM with ECC)
64 Kbytes (RAM with ECC)
- 32-bit system bus at 100 MHz
- 128-bit communication bus at 100 MHz
- 4 channels + 1 channel (for real-time port)
- Supports software and various interrupt-triggered DMA
- Serial flash ROM boot
- External memory boot
- External MCU boot
- 16-bit or 32-bit bus interface
- Page ROM / ROM / SRAM interface
- Synchronous burst memory interface
- Four chip selects for external SRAM
- 256-Mbyte (max) external memory space
- Programmable wait function
- 16-bit or 32-bit bus interface
- General-purpose interface for static memory
- Address space: 2 Mbytes (instruction RAM, data RAM, register area)
- Support serial interface compatible with SPI of the companies
- Support direct boot from serial memory device
- Support Fast Read, Fast Read Dual Output, Fast Read Dual I/O mode
- Direct layout in memory space
- 29 external interrupt pins
CMOS I/O: 96 pins (max.)
- Internal timer of Hardware RTOS
- Internal timer of CPU
- 4-channel timer array
- 32-bit counter & 32-bit data register
- Counter by external signal
R-IN32M3-CL
architecture
1. Overview
(1/2)
Page 2 of 104