Renesas R-IN32M3 Series User Manual page 20

R-IN32M3-CL User's Manual
2.1.2 External Memory Interface Pins
Pin Name
BUSCLK
CSZ0
CSZ1
CSZ2
CSZ3
Note4
A1/MA0
A2-A20/
Note4
MA1-MA19
A21-A27/
Note4
MA20-MA26
D0-D15/
Note1 Note4
MD0-MD15
D16-D31/
Note1 Note4
MD16-MD31
RDZ
WRSTBZ
WRZ0, WRZ1/
BENZ0, BENZ1
WRZ2, WRZ3/
BENZ2, BENZ3
WAITZ
Note2
WAITZ1-WAITZ3
Note3
BCYSTZ / ADVZ
Remark: Pins of the external memory interface pins other than BUSCLK are input pins while the
internal reset signal (HRESETZ) is at its active level.
Notes 1. While the synchronous burst access memory controller is in use, these signals are multiplexed
with the address signals if the ADMUXMODE pin is driven high.
ADMUXMODE = 0: MD0-MD31 (Separate address and data lines)
ADMUXMODE = 1: MD0-MD31/MA0-MA31 (Multiplexed address and data lines)
2. These pins are only available when the synchronous burst access memory controller is in use.
3. This pin functions as BCYSTZ when the asynchronous SRAM memory controller is in use and
as ADVZ when the synchronous burst access memory controller is in use.
4. This pin functions as A1-A27 and D0-D31 functions when the asynchronous SRAM memory
controller is in use and as MA0-MA26 and MD0-MD31 functions when the synchronous burst
access memory controller is in use.
R18UZ0005EJ0400
Dec. 28, 2018
I/O Function
O Bus clock output
O Chip select signal
output
O
O
O
O Address output
O
O
I/O Data bus
I/O
O Read strobe output
O Write strobe output
O Valid byte lane strobe
output
O
I Wait signal input
I Wait signal input
O Address valid output
Shared Pin Shared Port
- -
HCSZ -
HPGCSZ P44
- P51
- P50
HA1 P40
HA2-HA20 -
- RP21-
RP27
HD0-HD15 -
HD16-HD31 RP30-RP37
RP10-RP17
HRDZ -
HWRSTBZ -
HWRZ0, -
HWRZ1/
HBENZ0,
HBENZ1
HWRZ2, RP06,
HWRZ3/ RP07
HBENZ2,
HBENZ3
HWAITZ P41
- P45-P47
HBCYSTZ RP20
2. Pin Functions
Level during Level after
Active Reset
- Clock output
Low Hi-Z (High) High
Hi-Z (High)
- Hi-Z (High) Low
Hi-Z (Low)
Hi-Z (Low)
- Hi-Z (High)
Low Hi-Z (High) High
Low
Low
Hi-Z (High)
Low Hi-Z (High)
Low
Low
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