Process Bus Rear Connection; Communication Interfaces And Protocols - Hitachi Relion 650 Series Technical Manual

Section 15
IED physical connections
Connector
X8
X8
X8
X8
X8
X8
X8
X8
15.4.5

Process bus rear connection

Switchsync PWC600 can receive digital sampled values (voltage and/or current) via IEC
61850-9-2(LE) process bus at its X3/LAN2 A interface. Up to four logical merging units can be
connected, which are distinguished by their sampled values ID (svID). The specifications of X3 are
identical to X1 and X2.
Hardware synchronization of the sampled values is achieved by a 1PPS signal received on optical
input X10. Time synchronization via SNTP or IRIG-B cannot be used for this purpose.
Table 413: Process bus
Connector
X3
Table 414: Optical 1PPS signal
Connector
X10
For specification of the optical fibers to be used, see
15.4.6

Communication interfaces and protocols

Table 415: Supported station communication interfaces and protocols
Protocol
IEC 61850-8-1
HTTPS
● = Supported
426
Pin Signals
7 IRIG-B_GNDC
8 RS485_GND
9 RS485_RX -
10 RS485_TX +
11 RS485_TX -
12 RS485_SIGGND
13 IRIG-B +
14 IRIG-B_GND
EIA-485 communication is not enabled in this product.
If the 9-2 process values to Switchsync PWC600 originate from two or more
separate physical merging units, they should be synchronized to the same master.
Otherwise, occasional communication interruptions may occur.
Pin Signals
All 9-2LE
Pin Signals
Rx 1PPS
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Description
IRIG-B ground through capacitance
RS485 ground
RS485 receiver
RS485 transmitter
RS485 transmitter
Signal ground for RS485
Time synchronization input
IRIG-B ground
Description
Process bus: sampled values from one or more merging
units compliant to IEC 61850-9-2 (LE)
Description
Optical 1PPS signal from time synchronization master
Section 17.8.
Ethernet
100BASE-FX LC
1MRK 511 557-UEN Rev. A
GUID-60053C7B-4AD3-4DEC-9C47-BD2C2479516E v4
D0E7214T201305151403 v3
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