Frequency Lock Stage; Final Lock Stage; Notes On Operation; Irig-B Electrical Specifications - Novatech Bitronics M87X Series Manual

The M87x enters the Frequency Lock Mode after completing the first IRIG-B clock
correction. The M87x's clock is typically synchronized to within 1 millisecond of the true
IRIG-B time after the Time Lock Stage is completed.
5.7.7c Frequency Lock Stage
The M87x enters the Frequency Lock Stage of synchronization when it receives the third
valid clock correction value from the IRIG-B interface. At this time the M87x calculates a
crystal frequency correction constant based on the clock correction value. The crystal
frequency correction constant is stored in non-volatile memory to provide improved clock
accuracy during "Free Wheeling" . The crystal frequency correction constant along with the
clock correction value is used to slew the clock to synchronize to the IRIG-B source.
The Frequency Lock Stage requires approximately five minutes. Once the M87x slews its
clock with the correct crystal frequency correction constant, the M87x's clock is typically
synchronized to within 50 microseconds of the IRIG-B time source. The M87x then enters
the Final Lock Stage of synchronization.
5.7.7d Final Lock Stage
In the Final Lock Stage of synchronization, the M87x typically receives clock correction
values from the IRIG-B interface every five minutes. The M87x continues to make slight
adjustments to its crystal frequency correction constant to accommodate for small
frequency drifts due to age and temperature. At this point, the M87x clock is typically
synchronized to within less than 10 microseconds of the IRIG-B source.

5.7.8 Notes On Operation

1. A new crystal frequency correction constant will be written to non-volatile memory
every four hours while a valid IRIG-B connection exists.
2. The capacitor backed-up clock will be corrected every hour while a valid IRIG-B
connection exists.
3. Network Time Synchronization requests are refused while a valid IRIG-B connection
exists.

5.7.9 IRIG-B Electrical Specifications

Absolute Maximum Input Voltage:
Receiver Input Threshold Low:
Receiver Input Threshold High:
Receiver Input Hysteresis:
Receiver Input Resistance:
5.7.10 IRIG-B Port Wiring Instructions (Pulse Width Coded, IRIG-B master,

Demodulated)

The IRIG-B master can be connected to Ports P2, P3, or P4 of the M87x's Host CPU
module when IRIG-B signals of format IRIG B000, IRIG B001, or IRIG B003 are used. The
ML0021 August 15, 2018
-25 Volts to +25 Volts
0.8 Volts (min)
2.4 Volts (max)
0.6 Volts (typical)
5 kΩ (typical)
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