Table of Contents
Advertisement
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES)
Figure 12-2. Format of A/D Converter Mode Register 0 (ADM0)
Address: FF80H After reset: 00H R/W
Symbol
7
ADM0
ADCS0
ADCS0
0
1
TRG0
0
1
FR02
0
0
0
1
1
1
Other than above
EGA01
0
0
1
1
Notes 1. Set so that the A/D conversion time is 14 µ s or more.
2. Setting prohibited because A/D conversion time is less than 14 µ s.
Caution
When rewriting FR00 to FR02 to other than the same data, stop A/D conversion operations
once prior to performing rewrite.
Remarks 1. f
: Main system clock oscillation frequency
X
2. Figures in parentheses are for operation with f
196
6
5
TRG0
FR02
FR01
A/D conversion operation control
Stop conversion operation.
Enable conversion operation.
Software start/hardware start selection
Software start
Hardware start
FR01
FR00
0
0
144/f
0
1
120/f
1
0
96/f
0
0
72/f
0
1
60/f
1
0
48/f
Setting prohibited
EGA00
0
No edge detection
1
Falling edge detection
0
Rising edge detection
1
Both falling and rising edge detection
Preliminary User's Manual U16035EJ1V0UM
4
3
2
FR00
EGA01
Conversion time selection
(17.1 µ s)
X
(14.3 µ s)
X
Note 2
(Setting prohibited
)
X
Note 2
(Setting prohibited
)
X
Note 2
(Setting prohibited
)
X
Note 2
(Setting prohibited
)
X
External trigger signal, edge specification
= 8.38 MHz.
X
1
0
EGA00
0
Note 1
Advertisement
Table of Contents
