NEC mPD780024AS Series Preliminary User's Manual page 109

Figure 6-2. Format of 16-Bit Timer Mode Control Register 0 (TMC0)
Address FF60H After reset: 00H
Symbol 7 6 5
TMC0 0 0 0
TMC03 TMC02 TMC01
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
OVF0
0 Overflow not detected
1 Overflow detected
Cautions 1. Timer operation must be stopped before writing to bits other than the OVF0 flag.
2. Set the valid edge of the TI00/TO0/P70 pin with prescaler mode register 0 (PRM0).
3. If clear & start mode on match between TM0 and CR00 is selected, when the set value of
CR00 is FFFFH and the TM0 value changes from FFFFH to 0000H, OVF0 flag is set to 1.
Remark TO0: 16-bit timer/event counter output pin
TI00: 16-bit timer/event counter input pin
TM0: 16-bit timer counter 0
CR00: 16-bit timer capture/compare register 00
CR01: 16-bit timer capture/compare register 01
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0
R/W
4 3 2 1
0 TMC03 TMC02 TMC01
Operating mode
and clear mode selection
Operation stop
(TM0 cleared to 0)
Free-running mode
Clear & start on TI00 valid
edge
Clear & start on match
between TM0 and CR00
16-bit timer counter 0 (TM0) overflow detection
Preliminary User's Manual U16035EJ1V0UM
0
OVF0
TO0 output timing selection
No change
Match between TM0 and
CR00 or match between TM0
and CR01
Match between TM0 and
CR00, match between TM0
and CR01 or TI00 valid edge
—
Match between TM0 and
CR00 or match between TM0
and CR01
Match between TM0 and
CR00, match between TM0
and CR01 or TI00 valid edge
Interrupt request generation
Not generated
Generated on match
between TM0 and CR00, or
match between TM0 and
CR01
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