Table Of Contents - NEC mPD780024AS Series Preliminary User's Manual

CHAPTER 1 OUTLINE .......................................................................................................................
1.1 Features ....................................................................................................................................
1.2 Applications .............................................................................................................................
1.3 Ordering Information ...............................................................................................................
1.4 Pin Configuration (Top View) .................................................................................................
1.5 78K/0 Series Lineup .................................................................................................................
1.6 Block Diagram ..........................................................................................................................
1.7 Outline of Function ..................................................................................................................
CHAPTER 2 PIN FUNCTION ............................................................................................................
2.1 Pin Function List ......................................................................................................................
2.2 Description of Pin Functions ..................................................................................................
2.2.1 P00 to P03 (Port 0) ........................................................................................................................
2.2.2 P10 to P13 (Port 1) ........................................................................................................................
2.2.3 P20 to P25 (Port 2) ........................................................................................................................
2.2.4 P34 to P36 (Port 3) ........................................................................................................................
2.2.5 P40 to P47 (Port 4) ........................................................................................................................
2.2.6 P50 to P57 (Port 5) ........................................................................................................................
2.2.7 P70 to P75 (Port 7) ........................................................................................................................
2.2.8 AV .............................................................................................................................................
REF
2.2.9 AV ..............................................................................................................................................
DD
2.2.10 AV .............................................................................................................................................
SS
3.2.11 RESET ........................................................................................................................................
2.2.12 X1 and X2 ...................................................................................................................................
2.2.13 XT1 and XT2 ...............................................................................................................................
2.2.14 V and V
DD0
2.2.15 V and V
SS0
2.2.16 V (flash memory versions only) ................................................................................................
PP
2.2.17 IC (mask ROM version only) .......................................................................................................
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins .......................................
CHAPTER 3 CPU ARCHITECTURE .................................................................................................
3.1 Memory Spaces .......................................................................................................................
3.1.1 Internal program memory space ...................................................................................................
3.1.2 Internal data memory space ..........................................................................................................
3.1.3 Special function register (SFR) area .............................................................................................
3.1.4 External memory space ................................................................................................................
3.1.5 Data memory addressing ..............................................................................................................
3.2 Processor Registers ................................................................................................................
3.2.1 Control registers ............................................................................................................................
3.2.2 General-purpose registers ............................................................................................................
3.2.3 Special function register (SFR) .....................................................................................................
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CONTENTS
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DD1
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SS1
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