NEC mPD780024AS Series Preliminary User's Manual page 19

Figure No.
11-16 Analog Input Pin Connection ............................................................................................................... 187
11-17 A/D Conversion End Interrupt Request Generation Timing ................................................................. 188
11-18 Timing of Reading Conversion Result (When Conversion Result Is Undefined) .................................
11-19 Timing of Reading Conversion Result (When Conversion Result Is Normal) ...................................... 189
11-20 AV Pin Connection ........................................................................................................................... 190
DD
11-21 Example of Connecting Capacitor to AV
11-22 Internal Equivalent Circuit of Pins ANI0 to ANI3 .................................................................................. 191
11-23 Example of Connection If Signal Source Impedance Is High .............................................................. 192
12-1 Block Diagram of 10-Bit A/D Converter ............................................................................................... 193
12-2 Format of A/D Converter Mode Register 0 (ADM0) ............................................................................. 196
12-3 Format of Analog Input Channel Specification Register 0 (ADS0) ...................................................... 197
12-4 Format of External Interrupt Rising Edge Enable Register (EGP) and
External Interrupt Falling Edge Enable Register (EGN) ....................................................................... 197
12-5 Basic Operation of 10-Bit A/D Converter ............................................................................................. 199
12-6 Relationship Between Analog Input Voltage and A/D Conversion Result ............................................ 200
12-7 A/D Conversion by Hardware Start (When Falling Edge Is Specified) ................................................. 201
12-8 A/D Conversion by Software Start ....................................................................................................... 202
12-9 Overall Error ......................................................................................................................................... 203
12-10 Quantization Error ................................................................................................................................ 203
12-11 Zero Scale Offset ................................................................................................................................. 204
12-12 Full Scale Offset ................................................................................................................................... 204
12-13 Integral Linearity Error ......................................................................................................................... 204
12-14 Differential Linearity Error .................................................................................................................... 204
12-15 Example of Method of Reducing Current Consumption in Standby Mode ........................................... 206
12-16 Analog Input Pin Connection ............................................................................................................... 207
12-17 A/D Conversion End Interrupt Request Generation Timing ................................................................. 208
12-18 Timing of Reading Conversion Result (When Conversion Result Is Undefined) .................................
12-19 Timing of Reading Conversion Result (When Conversion Result Is Normal) ...................................... 209
12-20 AV Pin Connection ........................................................................................................................... 210
DD
12-21 Example of Connecting Capacitor to AV
12-22 Internal Equivalent Circuit of Pins ANI0 to ANI3 .................................................................................. 211
12-23 Example of Connection If Signal Source Impedance Is High .............................................................. 212
13-1 Block Diagram of Serial Interface (UART0) .......................................................................................... 214
13-2 Block Diagram of Baud Rate Generator .............................................................................................. 214
13-3 Format of Asynchronous Serial Interface Mode Register 0 (ASIM0) ................................................... 217
13-4 Format of Asynchronous Serial Interface Status Register 0 (ASIS0) .................................................. 218
13-5 Format of Baud Rate Generator Control Register 0 (BRGC0) ............................................................. 219
13-6 Baud Rate Error Tolerance (When k = 0), Including Sampling Errors .................................................. 227
13-7 Format of Transmit/Receive Data in Asynchronous Serial Interface .................................................... 228
LIST OF FIGURES (4/6)
Title
Pin ................................................................................... 190
REF
Pin ................................................................................... 210
REF
Preliminary User's Manual U16035EJ1V0UM
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