NEC mPD780024AS Series Preliminary User's Manual page 251

(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction
is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request
or upon application of RESET input.
IF0L, IF0H, and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are
combined to form 16-bit register IF0, they are set by a 16-bit memory manipulation instruction.
RESET input sets these registers to 00H.
Figure 15-2. Format of Interrupt Request Flag Register (IF0L, IF0H, IF1L)
Address: FFE0H After reset: 00H R/W
Symbol 7
IF0L STIF0
Address: FFE1H After reset: 00H R/W
Symbol 7
IF0H TMIF51
Address: FFE2H After reset: 00H R/W
Symbol 7
IF1L 0
XXIFX
0
1
Cautions 1. The WDTIF flag is R/W enabled only when the watchdog timer is used as the interval timer.
If watchdog timer mode 1 is used, set the WDTIF flag to 0.
2. Be sure to set bit 2 of IF0H and bits 3 to 7 of IF1L to 0.
3. When operating a timer, serial interface, or A/D converter after standby release, run it once
after clearing an interrupt request flag. An interrupt request flag may be set by noise.
4. When an interrupt is acknowledged, the interrupt request flag is automatically cleared, and
then processing of the interrupt routine is started.
CHAPTER 15 INTERRUPT FUNCTIONS
6 5
SRIF0 SERIF0 PIF3
6 5
TMIF50 TMIF01 TMIF00
6 5
0 0
No interrupt request signal is generated
Interrupt request signal is generated, interrupt request status
Preliminary User's Manual U16035EJ1V0UM
4 3 2
PIF2 PIF1
4 3 2
WTIIF 0
4 3 2
0 0 KRIF
Interrupt request flag
1 0
PIF0 WDTIF
1 0
CSIIF31 CSIIF30
1 0
WTIF ADIF0
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