Configuration Of A/D Converter - NEC mPD780024AS Series Preliminary User's Manual

CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES)

11.2 Configuration of A/D Converter

The A/D converter consists of the following hardware.
Item
Analog input
Registers
Control registers
(1) Successive approximation register (SAR)
This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from
the series resistor string, and holds the result from the most significant bit (MSB).
When up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are transferred to
the A/D conversion result register 0 (ADCR0).
(2) A/D conversion result register 0 (ADCR0)
The ADCR0 is an 8-bit register that stores the A/D conversion result. Each time A/D conversion ends, the
conversion result is loaded from the successive approximation register.
ADCR0 is read by an 8-bit memory manipulation instruction.
RESET input sets ADCR0 to 00H.
Caution When writing is performed to the A/D converter mode register 0 (ADM0) and analog input
channel specification register 0 (ADS0), the contents of ADCR0 may become undefined. Read
the conversion result following conversion completion before writing to ADM0, ADS0. Using
a timing other than the above may cause an incorrect conversion result to be read.
(3) Sample & hold circuit
The sample & hold circuit samples each analog input signal sequentially applied from the input circuit, and sends
it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion.
(4) Voltage comparator
The voltage comparator compares the analog input to the series resistor string output voltage.
(5) Series resistor string
The series resistor string is connected between AV
the analog input.
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Table 11-1. Configuration of A/D Converter
4 channels (ANI0 to ANI3)
Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)
A/D converter mode register 0 (ADM0)
Analog input channel specification register 0 (ADS0)
External interrupt rising edge enable register (EGP)
External interrupt falling edge enable register (EGN)
and AV
REF
Preliminary User's Manual U16035EJ1V0UM
Configuration
, and generates a voltage to be compared to
SS