NEC mPD780024AS Series Preliminary User's Manual page 292

Instruction
Mnemonic
Group
Bit
AND1 CY, saddr.bit
manipu-
CY, sfr.bit
late
CY, A.bit
CY, PSW.bit
CY, [HL].bit
OR1 CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
XOR1 CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW. bit
CY, [HL].bit
SET1 saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CLR1 saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
SET1 CY
CLR1 CY
NOT1 CY
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
292
CHAPTER 19 INSTRUCTION SET
Clock
Operands Byte
Note 1
3 6
3 –
2 4
3 –
2 6
3 6
3 –
2 4
3 –
2 6
3 6
3 –
2 4
3 –
2 6
2 4
3 –
2 4
2 –
2 6
2 4
3 –
2 4
2 –
2 6
1 2
1 2
1 2
Preliminary User's Manual U16035EJ1V0UM
Operation
Note 2
CY ← CY (saddr.bit)
7
CY ← CY sfr.bit
7
CY ← CY A.bit
–
CY ← CY PSW.bit
7
CY ← CY (HL).bit
7 + n
CY ← CY (saddr.bit)
7
CY ← CY sfr.bit
7
CY ← CY A.bit
–
CY ← CY PSW.bit
7
CY ← CY (HL).bit
7 + n
CY ← CY
7 (saddr.bit)
CY ← CY
7 sfr.bit
CY ← CY
– A.bit
CY ← CY
7 PSW.bit
CY ← CY
7 + n (HL).bit
(saddr.bit) ← 1
6
sfr.bit ← 1
8
A.bit ← 1
–
PSW.bit ← 1
6
(HL).bit ← 1
8 + n + m
(saddr.bit) ← 0
6
sfr.bit ← 0
8
A.bit ← 0
–
PSW.bit ← 0
6
(HL).bit ← 0
8 + n + m
CY ← 1
–
CY ← 0
–
CY ← CY
–
) selected by the processor clock control
CPU
Flag
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
× × ×
× × ×
1
0
×