NEC mPD780024AS Series Preliminary User's Manual page 171

CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES)
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ADTRG/INTP3/P03
3
ADS02 ADS01 ADS00 ADSC0 TRG0 FR02 FR01 FR00 EGA01 EGA00
Analog input channel
specification register 0 (ADS0)
Note The valid edge is specified by bit 3 of the EGP and EGN registers (see Figure 11-4 Format of External
Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register
(EGN)).
Figure 11-1. Block Diagram of 8-Bit A/D Converter
Sample & hold circuit
Edge
detector
Edge
detector
Note
Trigger enable
Internal bus
Preliminary User's Manual U16035EJ1V0UM
Voltage comparator
Successive
approximation
register (SAR)
Controller
A/D conversion result
register 0 (ADCR0)
A/D converter
mode register 0 (ADM0)
Series resistor string
AV
DD
AV
REF
AV
SS
INTAD0
INTP3
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