NEC mPD780024AS Series Preliminary User's Manual page 167

CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Figure 10-2. Format of Clock Output Select Register (CKS)
Address: FF40H After reset: 00H R/W
Symbol 7
CKS BZOE BCS1
BZOE
0 Stop clock division circuit operation. BUZ fixed to low level.
1 Enable clock division circuit operation. BUZ output enabled.
BCS1 BCS0
0
0
1
1
CLOE
0 Stop clock division circuit operation. PCL fixed to low level.
1 Enable clock division circuit operation. PCL output enabled.
CCS3 CCS2
0
0
0
0
0
0
0
0
1
Other than above
Remarks 1. f : Main system clock oscillation frequency
X
2. f : Subsystem clock oscillation frequency
XT
3. Figures in parentheses are for operation with f
6 5 4
BCS0 CLOE
BUZ output enable/disable specification
10
0 f /2 (8.18 kHz)
X
11
1 f /2 (4.09 kHz)
X
12
0 f /2 (2.04 kHz)
X
13
1 f /2 (1.02 kHz)
X
PCL output enable/disable specification
CCS1 CCS0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
Preliminary User's Manual U16035EJ1V0UM
3 2
CCS3 CCS2
BUZ output clock selection
PCL output clock selection
f (8.38 MHz)
X
f /2 (4.19 MHz)
X
2
f /2 (2.09 MHz)
X
3
f /2 (1.04 MHz)
X
4
f /2 (524 kHz)
X
5
f /2 (262 kHz)
X
6
f /2 (131 kHz)
X
7
f /2 (65.5 kHz)
X
f (32.768 kHz)
XT
Setting prohibited
= 8.38 MHz or f = 32.768 kHz.
X XT
1 0
CCS1 CCS0
167