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Figure No.
7-7.
CR0m Capture Operation with Rising Edge Specified .....................................................................
7-8.
Timing of Pulse Width Measurement Operation by Free-Running Counter
(with Both Edges Specified) ..............................................................................................................
7-9.
16-Bit Timer Register Start Timing ....................................................................................................
7-10.
Capture Register Data Retention Timing ..........................................................................................
8-1.
Timer 1 (TM1) Block Diagram ...........................................................................................................
8-2.
Timer Clock Select Register 1 (TCL1) Format ..................................................................................
8-3.
8-Bit Timer Mode Control Register 1 (TMC1) Format .......................................................................
8-4.
Interval Timer Operation Timings ......................................................................................................
8-5.
Timer 1 Start Timing ..........................................................................................................................
8-6.
Timing after Compare Register Change during Timer Count Operation ...........................................
9-1.
Timer 2 (TM2) Block Diagram ...........................................................................................................
9-2.
Timer 3 (TM3) Block Diagram ...........................................................................................................
9-3.
Timer Clock Select Register 2 (TCL2) Format ..................................................................................
9-4.
Timer Clock Select Register 3 (TCL3) Format ..................................................................................
9-5.
8-Bit Timer Mode Control Register n (TMCn) Format .......................................................................
9-6.
Interval Timer Operation Timings ......................................................................................................
9-7.
External Event Counter Operation Timings (with Rising Edge Specified) ........................................
9-8.
PWM Output Operation Timing .........................................................................................................
9-9.
Timing of Operation by Change of CRn ............................................................................................
9-10.
Timer n Start Timing ..........................................................................................................................
9-11.
Timing after Compare Register Change during Timer Count Operation ...........................................
10-1.
Watch Timer Block Diagram .............................................................................................................
10-2.
Watch Timer Mode Control Register (WTM) Format ........................................................................
10-3.
Operation Timing of Watch Timer/Interval Timer ...............................................................................
11-1.
Watchdog Timer Block Diagram .......................................................................................................
11-2.
Watchdog Timer Clock Select Register (WDCS) Format ..................................................................
11-3.
Watchdog Timer Mode Register (WDTM) Format ............................................................................
12-1.
Clock Output Control Circuit Block Diagram .....................................................................................
12-2.
Clock Output Selection Register (CKS) Format ................................................................................
12-3.
Port Mode Register 6 (PM6) Format .................................................................................................
12-4.
Remote Control Output Application Example ...................................................................................
13-1.
A/D Converter Block Diagram ...........................................................................................................
13-2.
Power-Fail Detection Function Block Diagram .................................................................................
13-3.
A/D Converter Mode Register (ADM1) Format .................................................................................
13-4.
Analog Input Channel Specification Register (ADS1) Format ..........................................................
13-5.
Power-Fail Compare Mode Register (PFM) Format .........................................................................
13-6.
Basic Operation of 8-Bit A/D Converter ............................................................................................
13-7.
Relation between Analog Input Voltage and A/D Conversion Result ................................................
18
LIST OF FIGURES (2/4)
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