NEC mPD780973 Series Preliminary User's Manual page 180

(d) Reception
The receive operation is enabled when "1" is set to bit 6 (RXE) of the asynchronous serial interface mode
register (ASIM), and input via the RxD pin is sampled.
The serial clock specified by ASIM is used when sampling the RxD pin.
When the RxD pin goes low, the 5-bit counter begins counting and the start timing signal for data sampling
is output when half of the specified baud rate time has elapsed. If sampling the RxD pin input with this start
timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and
starts counting and data sampling begins. After the start bit is recognized, the character data, parity bit,
and one-bit stop bit are detected, at which point reception of one data frame is completed.
Once reception of one data frame is completed, the receive data in the shift register is transferred to the
receive buffer register (RXB) and a receive completion interrupt (INTSR) occurs.
Even if an error has occurred, the receive data in which the error occurred is still transferred to RXB. INTSR
occurs if bit 1 (ISRM) of ASIM is cleared to 0 on occurrence of an error. If the ISRM bit is set to 1, INTSR
does not occur (see Figure 14-9).
If the RXE bit is reset (to "0") during a receive operation, the receive operation is stopped immediately. At
this time, the contents of RXB and ASIS do not change, nor does INTSR or INTSER occur.
Figure 14-8 shows the timing of the asynchronous serial interface receive completion interrupt.
Figure 14-8. Timing of Asynchronous Serial Interface Receive Completion Interrupt
RxD (input)
INTSR
Caution Be sure to read the contents of the receive buffer register (RXB) even when a receive
error has occurred. Overrun errors will occur during the next data receive operations
and the receive error status will remain until the contents of RXB are read.
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CHAPTER 14 SERIAL INTERFACE UART
START D0 D1 D2 D6 D7 Parity STOP