Table of Contents
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Table No.
2-1.
Pin Input/Output Circuit Types ..........................................................................................................
3-1.
Internal Memory Capacity .................................................................................................................
3-2.
Vector Table ......................................................................................................................................
3-3.
Internal High-Speed RAM Capacity ..................................................................................................
3-4.
Internal High-Speed RAM Area ........................................................................................................
3-5.
Special Function Register List ..........................................................................................................
5-1.
Port Functions ...................................................................................................................................
5-2.
Port Configuration .............................................................................................................................
5-3.
Port Mode Register and Output Latch Settings when Using Alternate Functions .............................
6-1.
Clock Generator Configuration .........................................................................................................
6-2.
Relation between CPU Clock and Minimum Instruction Execution Time ..........................................
6-3.
Maximum Time Required for Switching CPU Clock ..........................................................................
7-1.
Timer/Event Counter Operations ......................................................................................................
7-2.
Timer 0 Configuration .......................................................................................................................
8-1.
Timer 1 Configuration .......................................................................................................................
9-1.
Timers 2 and 3 Configurations ..........................................................................................................
10-1.
Interval Timer Interval Time ..............................................................................................................
10-2.
Watch Timer Configuration ...............................................................................................................
10-3.
Interval Timer Interval Time ..............................................................................................................
11-1.
Watchdog Timer Runaway Detection Time .......................................................................................
11-2.
Interval Time .....................................................................................................................................
11-3.
Watchdog Timer Configuration .........................................................................................................
11-4.
Watchdog Timer Runaway Detection Time .......................................................................................
11-5.
Interval Timer Interval Time ..............................................................................................................
12-1.
Clock Output Control Circuit Configuration .......................................................................................
13-1.
A/D Converter Configuration .............................................................................................................
14-1.
UART Configuration ..........................................................................................................................
14-2.
Relation between 5-bit Counter's Source Clock and "n" Value .........................................................
14-3.
Relation between Main System Clock and Baud Rate .....................................................................
14-4.
Causes of Receive Errors .................................................................................................................
15-1.
SIO3 Configuration ...........................................................................................................................
LIST OF TABLES (1/2)
Title
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43
44
48
52
74
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85
89
90
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100
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112
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134
134
136
140
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143
144
145
150
166
175
176
181
184
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