NEC mPD780973 Series Preliminary User's Manual page 228

(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction
is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request
or upon application of RESET input.
IF0L, IF0H, and IF1L are set with a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are
combined to form 16-bit register IF0, they are set with a 16-bit memory manipulation instruction.
RESET input sets these registers to 00H.
Figure 19-2. Interrupt Request Flag Register (IF0L, IF0H, IF1L) Format
Address: FFE0H After Reset: 00H R/W
Symbol 7
IF0L PIF1
Address: FFE1H After Reset: 00H R/W
Symbol 7
IF0H TMIF3
Address: FFE2H After Reset: 00H R/W
Symbol 7
IF1L 0
XXIFX
0
1
Cautions 1. The WDTIF flag is R/W enabled only when the watchdog timer is used as the interval timer.
If watchdog timer mode 1 is used, set the WDTIF flag to 0.
2. Be sure to set 0 to IF1L bits 3 to 7.
228
CHAPTER 19 INTERRUPT FUNCTIONS
6 5
PIF0 TMIF02 TMIF01
6 5
TMIF2 TMIF1 STIF
6 5
0 0
No interrupt request signal is generated
Interrupt request signal is generated, interrupt request status
4 3 2
TMIF00 OVFIF
4 3 2
SRIF SERIF
4 3 2
0 0 WTIF
Interrupt Request Flag
1 0
ADIF WDTIF
1 0
CSIIF PIF2
1 0
WTIIF WEIF