NEC mPD780973 Series Preliminary User's Manual page 176

• Error tolerance range for baud rates
The tolerance range for baud rates depends on the number of bits per frame and the counter's division
rate [1/(16 + k)].
Table 14-3 describes the relation between the main system clock and the baud rate and Figure 14-5 shows
an example of a baud rate error tolerance range.
Table 14-3. Relation between Main System Clock and Baud Rate
Remark f
Figure 14-5. Error Tolerance (when k = 0) including Sampling Errors
Basic timing
(clock cycle T)
High-speed clock
(clock cycle T')
enabling normal
reception
Low-speed clock
(clock cycle T")
enabling normal
reception
Remark T : 5-bit counter's source clock cycle
Baud rate error tolerance (when k = 0) =
176
CHAPTER 14 SERIAL INTERFACE UART
Baud rate
(bps)
BRGC Set Value
600 7BH
1200 6BH
2400 5BH
4800 4BH
9600 3BH
19200 2BH
31250 21H
38400 1BH
76800 0BH
115200 01H
: Main system clock oscillation frequency
X
32T 64T 256T
START D0
START D0
30.45T 60.9T
START D0
33.55T 67.1T
±15.5
320
f = 8.386 MHz
X
Error (%)
1.10
1.10
1.10
1.10
1.10
–1.3
1.10
1.10
1.10
1.03
Ideal
sampling
point
288T 320T
304T
D7 P
STOP
15.5T
D7 P
STOP
304.5T
15.5T
D7 P
301.95T
× 100 = 4.8438 (%)
352T
336T
Sampling error
0.5T
STOP
335.5T