NEC mPD780973 Series Preliminary User's Manual page 270

Instruction
Mnemonic
Group
ADDW AX, #word
16-bit
SUBW AX, #word
operation
CMPW AX, #word
MULU X
Multiply/
divide
DIVUW C
r
INC
saddr
Increment/ r
DEC
decrement
saddr
INCW rp
DECW rp
ROR A, 1
ROL A, 1
RORC A, 1
ROLC A, 1
Rotate
ROR4 [HL]
ROL4 [HL]
ADJBA
BCD
adjust
ADJBS
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
Bit
CY, [HL].bit
MOV1
manipu-
saddr.bit, CY
late
sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
270
CHAPTER 23 INSTRUCTION SET
Clock
Operands Byte
Note 1
3 6
3 6
3 6
2 16
2 25
1 2
2 4
1 2
2 4
1 4
1 4
1 2
1 2
1 2
1 2
2 10
2 10
2 4
2 4
3 6
3 –
2 4
3 –
2 6
3 6
3 –
2 4
3 –
2 6
Operation
Note 2
AX, CY ← AX + word
–
AX, CY ← AX – word
–
– AX – word
AX ← A × X
–
AX (Quotient), C (Remainder) ← AX ÷ C
–
r ← r + 1
–
(saddr) ← (saddr) + 1
6
r ← r – 1
–
(saddr) ← (saddr) – 1
6
rp ← rp + 1
–
rp ← rp – 1
–
← A ← A
– (CY, A , A
7 0 m – 1
← A ← A
– (CY, A , A
0 7 m + 1
(CY ← A ← CY, A
– , A
0 7
(CY ← A ← CY, A
– , A
7 0
← (HL)
A , (HL)
3 – 0 3 – 0 7 – 4
12
← (HL)
(HL)
3 – 0 7 – 4
← (HL)
A , (HL)
3 – 0 7 – 4 3 – 0
12
← (HL)
(HL)
7 – 4 3 – 0
Decimal Adjust Accumulator after
–
Addition
Decimal Adjust Accumulator after
–
Subtract
CY ← (saddr.bit)
7
CY ← sfr.bit
7
CY ← A.bit
–
CY ← PSW.bit
7
CY ← (HL).bit
7
(saddr.bit) ← CY
8
sfr.bit ← CY
8
A.bit ← CY
–
PSW.bit ← CY
8
(HL).bit ← CY
8
) selected by the processor clock control
CPU
Flag
Z AC CY
× × ×
× × ×
× × ×
× ×
× ×
× ×
× ×
) × 1 time ×
m
) × 1 time ×
m
← A ) × 1 time ×
m – 1 m
← A ) × 1 time ×
m + 1 m
← A
,
3 – 0
← A
,
3 – 0
× × ×
× × ×
×
×
×
×
×
× ×