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Figure 14-4. Baud Rate Generator Control Register (BRGC) Format
Address: FF87H After Reset: 00H
Symbol
7
BRGC
0
TPS2
0
0
0
0
1
1
1
1
MDL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Cautions 1. Writing to BRGC during a communication operation may cause abnormal output from
the baud rate generator and disable further communication operations. Therefore, do
not write to BRGC during a communication operation.
2. Bit 7 must be set to 0.
Remarks 1. f
: Source clock for 5-bit counter
SCK
: Value set via TPS0 to TPS2 (1 ≤ n ≤ 8)
2. n
: Value set via MDL0 to MDL3 (0 ≤ k ≤ 14)
3. k
170
CHAPTER 14 SERIAL INTERFACE UART
R/W
6
5
4
TPS2
TPS1
TPS0
TPS1
TPS0
0
0
f
/2
X
2
0
1
f
/2
X
3
1
0
f
/2
X
4
1
1
f
/2
X
5
0
0
f
/2
X
6
0
1
f
/2
X
7
1
0
f
/2
X
8
1
1
f
/2
X
MDL2
MDL1
MDL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
3
2
MDL3
MDL2
Source Clock Selection for 5-bit Counter
Input Clock Selection for Baud Rate Generator
f
/16
SCK
f
/17
SCK
f
/18
SCK
f
/19
SCK
f
/20
SCK
f
/21
SCK
f
/22
SCK
f
/23
SCK
f
/24
SCK
f
/25
SCK
f
/26
SCK
f
/27
SCK
f
/28
SCK
f
/29
SCK
f
/30
SCK
Setting prohibited
1
0
MDL1
MDL0
(f
= 8.38 MHz)
X
n
1
2
3
4
5
6
7
8
k
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
—
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