Xilinx XtremeDSP Spartan-3A DSP 3400A HW-SD3400A-DSP-DB-UNI-G User Manual page 24

Chapter 1: Introduction
24
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Table 1-9: FMC #1 Expansion Connector Pin Assignments (1) (Cont'd)
FMC Pin FPGA Pin
C14 K5
C15 K4
C16 NC
C17 NC
C18 J5
C19 J4
C20 NC
C21 NC
C22 K3
C23 K2
C24 NC
C25 NC
C26 T5
C27 U4
C28 NC
C29 NC
(1)
C30 AF23
(1)
C31 AE25
C32 NC
C33 NC
C34 NC
C35 NC
C36 NC
C37 NC
C38 NC
C39 NC
C40 NC
2
1. I C bus connected to FPGA through I
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Signal FMC Pin
0_LA10_P D14
0_LA10_N D15
GND D16
GND D17
0_LA14_P D18
0_LA14_N D19
GND D20
GND D21
0_LA18_P D22
0_LA18_N D23
GND D24
GND D25
0_LA27_P D26
0_LA27_N D27
GND D28
GND D29
D30
SCL
SDA D31
GND D32
GND D33
GA0 (ground) D34
12P0V D35
GND D36
12P0V
D37
GND D38
3P3V D39
GND D40
2
C mux (U1). Mux needs to be configured for the proper channel
Spartan-3A DSP 3400A Edition User Guide
FPGA Pin Signal
E3 0_LA09_P
F4 0_LA09_N
NC GND
K7 0_LA13_P
J6 0_LA13_N
NC GND
N9 0_LA17_P_CC
P10 0_LA17_N_CC
NC GND
N5 0_LA23_P
N4 0_LA23_N
NC GND
N1 0_LA26_P
N2 0_LA26_N
NC GND
A25 TCK
E23
TDI
NC TDO
NC 3P3VAUX
D4 TMS
NC TRSTL
NC GA1 (GND)
NC 3P3V
GND
NC
NC 3P3V
NC GND
NC 3P3V
UG498 (v2.2) November 17, 2008
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