Xilinx XtremeDSP Spartan-3A DSP 3400A HW-SD3400A-DSP-DB-UNI-G User Manual page 39

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Spartan-3A DSP 3400A Edition User Guide
UG498 (v2.2) November 17, 2008
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Table 1-28: FPGA DDR2 Interface Pin Assignments
FPGA Pin
Description
AA25
DDR2_A_0
AA22
DDR2_A_1
AB26
DDR2_A_2
Y21
DDR2_A_3
AC24
DDR2_A_4
AA24
DDR2_A_5
AD26
DDR2_A_6
AE26
DDR2_A_7
AB23
DDR2_A_8
AC25
DDR2_A_9
W21
DDR2_A_10
AD25
DDR2_A_11
AC23
DDR2_A_12
V19
DDR2_A_13
V21
DDR2_0_BA_0
AA23
DDR2_0_BA_1
AC26
DDR2_0_BA_2
U20
DDR2_0_CAS_B
U18
DDR2_0_CK0_N
U19
DDR2_0_CK0_P
D26
DDR2_0_CK1_N
E26
DDR2_0_CK1_P
P25
DDR2_0_DM_0
N18
DDR2_0_DM_1
M22
DDR2_0_DM_2
M18
DDR2_0_DM_3
N19
DDR2_0_DQS0_N
P18
DDR2_0_DQS0_P
K26
DDR2_0_DQS1_N
K25
DDR2_0_DQS1_P
J22
DDR2_0_DQS2_N
J23
DDR2_0_DQS2_P
L17
DDR2_0_DQS3_N
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Spartan-3A DSP 3400A Edition Board Hardware
FPGA Pin
Description
N24
DDR2_0_DQ_0
M26
DDR2_0_DQ_1
M25
DDR2_0_DQ_2
P23
DDR2_0_DQ_3
N21
DDR2_0_DQ_4
P22
DDR2_0_DQ_5
P20
DDR2_0_DQ_6
P26
DDR2_0_DQ_7
M20
DDR2_0_DQ_8
L24
DDR2_0_DQ_9
J25
DDR2_0_DQ_10
J26
DDR2_0_DQ_11
N17
DDR2_0_DQ_12
N20
DDR2_0_DQ_13
M23
DDR2_0_DQ_14
M21
DDR2_0_DQ_15
G24
DDR2_0_DQ_16
G23
DDR2_0_DQ_17
K22
DDR2_0_DQ_18
M19
DDR2_0_DQ_19
F24
DDR2_0_DQ_20
K23
DDR2_0_DQ_21
K21
DDR2_0_DQ_22
L22
DDR2_0_DQ_23
F23
DDR2_0_DQ_24
E24
DDR2_0_DQ_25
K20
DDR2_0_DQ_26
L20
DDR2_0_DQ_27
G22
DDR2_0_DQ_28
F25
DDR2_0_DQ_29
K18
DDR2_0_DQ_30
K19
DDR2_0_DQ_31
C25
DDR2_LOOP_OUT
39

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