Xilinx XtremeDSP Spartan-3A DSP 3400A HW-SD3400A-DSP-DB-UNI-G User Manual page 35

R
Spartan-3A DSP 3400A Edition User Guide
UG498 (v2.2) November 17, 2008
Downloaded from Elcodis.com electronic components distributor
31. User-defined DIP Switches
Eight general-purpose, active-high DIP switches (S3) are connected to the user I/O
pins of the FPGA.
Table 1-22: User-defined DIP Switch FPGA Pin Assignments
Switch No. FPGA Pin
1 R26
2 R25
3 T23
4 R24
5 T18
6 R22
7 R21
8 R20
32. User-defined LEDs
Eight general-purpose, active-high LEDs (DS10-DS17) are connected to the user I/O
pins of the FPGA.
Table 1-23: User-defined LED FPGA Pin Assignments
LED No. FPGA Pin
1 (DS10)
2 (DS11)
3 (DS12)
4 (DS13)
5 (DS14)
6 (DS15)
7 (DS16)
8 (DS17)
BUS_ERROR_1 (DS22)
BUS_ERROR_2 (DS23)
www.xilinx.com
Spartan-3A DSP 3400A Edition Board Hardware
Description
FPGA_DIP_SW0
FPGA_DIP_SW1
FPGA_DIP_SW2
FPGA_DIP_SW3
FPGA_DIP_SW4
FPGA_DIP_SW5
FPGA_DIP_SW6
FPGA_DIP_SW7
Description
W23 GPIO_LED_0
V22 GPIO_LED_1
V25 GPIO_LED_2
V24 GPIO_LED_3
V23 GPIO_LED_4
U23 GPIO_LED_5
U22 GPIO_LED_6
T24 GPIO_LED_7
C26 BUS ERROR LED 1
Y24 BUS ERROR LED 2
35