Xilinx XtremeDSP Spartan-3A DSP 3400A HW-SD3400A-DSP-DB-UNI-G User Manual page 31

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Spartan-3A DSP 3400A Edition User Guide
UG498 (v2.2) November 17, 2008
Downloaded from Elcodis.com electronic components distributor
20. Clock Generator
IDT IDT5V9885PFGI. Used to generate different clocks on the Spartan-3A DSP 3400A
Edition board. Table 1-14
generator can be programmed through the I
page 42) or through a JTAG interface using connector P2 (see
"Programming the IDT Clock
Table 1-14: Clock Generator Default Settings
Clock FPGA Pin (if
Generator Connected to
Output FPGA)
1 NA
2 NA
3 NA
4_P NA
4_N AE13
5_P AA13
5_N Y13
6 AF13
2
21. 64-Kb I C EEPROM
2
The I C EEPROM 24LC64 can be used to store non-volatile data, for example, an
Ethernet MAC address. The EEPROM is accessible through the I
Addressing"). The EEPROM write-protect is disabled on the board. I
resistors are provided on the board.
2
The I C bus is extended to the FMC expansion connector so that the board can access
2
additional I C devices and share the I
2
Table 1-15: I C FPGA Pin Assignments
2
I C Signal FPGA Pin
(1)
IIC_SCLK AF23
(1)
IIC_SDAT AE25
2
1. I C bus connected to FPGA through I
to be configured for the proper channel.
2
22. I C Fan Controller and Temperature/voltage Monitor
Onboard temperature and voltage monitoring and control are handled by an Analog
Devices ADT7476A device. This device is controlled through I
Addressing") and do the following:
♦
Measure the voltage of the 5-V, 3.3-V, 1.8-V, and 1.0-V supplies
♦
Measure the FPGA temperature through the DXP/DXN pins on the FPGA
♦
Measure ambient temperature
♦
Read power good status signals from the 2.5-V linear regulators
www.xilinx.com
Spartan-3A DSP 3400A Edition Board Hardware
summarizes the default settings of output clocks. The clock
2
C interface (see
Chip"for information).
Default
Frequency
25 MHz Ethernet PHY clock
14.31818 MHz Audio codec clock
12 MHz USB clock
31.25 MHz System ACE clock
31.25 MHz FPGA clock
125 MHz FPGA LVDS differential clock P
125 MHz FPGA LVDS differential clock N
27 MHz FPGA clock
2
C controller in the FPGA.
Description
2
I C clock
2
I C data
2
C MUX (U1). MUX needs
"I2C Bus Addressing,"
Chapter 3,
Clock Usage
2
C bus (see "I2C Bus
2
C bus pull-up
2
C ("I2C Bus
31