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Table 1-4: Default Ethernet PHY Configuration
Configuration Pin
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
Spartan-3A DSP 3400A Edition User Guide
UG498 (v2.2) November 17, 2008
Downloaded from
Elcodis.com
electronic components distributor
7. Board Flash PROM
Xilinx XCF32P. This flash PROM is used to program the development board FPGA.
The flash PROM can hold up to two distinct configuration images (up to four
compressed configuration images) that can be accessed through the configuration DIP
switches. Requires that you use the same configuration DIP switches to configure the
FPGA from the platform flash PROM. See
detailed information.
8. Ethernet PHY
Marvell Alaska 88E1111 PHY device. This PHY supports 10Base-T, 100Base-TX, and
1000Base-T (Gigabit) Ethernet. The PHY is connected to the board's Ethernet connector
("9. Ethernet
Port"). The Ethernet PHY is initialized under its default configuration
when the development board is turned on or reset. Jumper JP2 selects whether the
PHY's default is RGMII mode (pins 2-3) or GMII mode (pins 1-2).
default configuration of the Ethernet PHY, which can be modified through software.
Table 1-5
identifies the FPGA pin assignments for building new FPGA files.
Board Connection
V
2.5 V
PHYADR[2] = 1
cc
Ground
ENA_PAUSE = 0
V
2.5 V
ANEG[3] = 1
cc
V
2.5 V
ANEG[0] = 1
cc
V
2.5 V or
HCWCFG_MODE
cc
LED_DUPLEX
[2] = 0 or 1
V
2.5 V
DIS_FC = 1
cc
LED_RX
SEL_BDT = 0
Table 1-5: Ethernet Interface Pin Assignments
FPGA Pin
Description
AB13
PHY_COL
AC10
PHY_CRS
AC6
PHY_INT
AE4
PHY_MDC
AD6
PHY_MDIO
AE9
PHY_RESET_N
AC17
PHY_RXCTL_RXDV
AF17
PHY_RXD_0
AD9
PHY_RXD_1
Spartan-3A DSP 3400A Edition Board Hardware
"33. Configuration DIP Switches"
Bit 2
Bit 1
PHYADR[1] = 1
PHYADR[4] = 0
ANEG[2] = 1
ENA_XC = 1
HCWCFG_MODE
[1] = 1
DIS_SLEEP = 1
INT_POL = 1
FPGA Pin
AA14
AC13
AE17
W13
V12
AB9
W12
AC9
AA12
www.xilinx.com
for
Table 1-4
defines the
Bit 0
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
HCWCFG_MODE
[0] = 1
HCWCFG_MODE
[3] = 1
50/75 ohm = 0
(50 ohm termination)
Description
PHY_RX_CLK
PHY_RX_ER
PHY_TXCTL_TXEN
PHY_TXC_GTXCLK
PHY_TXD_0
PHY_TXD_1
PHY_TXD_2
PHY_TXD_3
PHY_TXD_4
19
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