Table of Contents
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Revision History
The following table shows the revision history for this document.
Date
6/2007
7/2007
7/2007
8/2007
9/2007
10/2007
10/2007
1/2008
11/17/08
UG498 (v2.2) November 17, 2008
Downloaded from
Elcodis.com
electronic components distributor
Version
0.1
Preliminary version.
0.2
Added appendix.
0.3
Updated version for final review.
1.0
• Updated FMC information.
• Updated support information.
• Added FPGA pin assignments for DDR2 interface.
• Added FPGA pin assignments for USB/System ACE interface.
1.1
Added Known Issues section: Limitation of DDR2 clock rate to 133 MHz; Soft Touch
connector not compliant with Agilent probes; FMC connector is in violation of some
rules of the standard.
1.2
• Updated Table 20 (Serial Port FPGA Pin Assignments) and modified layout to reflect
change in corporate image.
• Updated for XtremeDSP Spartan-3A DSP Development Board Revision D.
2.0
Updated for XtremeDSP Spartan-3A DSP Development Board Revision.
2.1
Updated with new clock generator configuration.
2.2
• Ported to Xilinx template.
• Updated Table 12 (FMC Pin G3 is attached to net 1_CLK0_C2M_N).
• Updated to account for PS6 being the power supply used for FMC 2 adjustable voltage.
Revision
www.xilinx.com
Spartan-3A DSP 3400A Edition User Guide
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