Spi Interfaces - Quectel Smart LTE Module Series Hardware Design

Table 16: Pin Definition of I2S Interface
Pin Name Pin No
I2S_MCLK 234
I2S_1_SCK 212
I2S_1_WS 156
I2S_1_D0 154
I2S_1_D1 155
I2S_1_D2 213
I2S_1_D3 214

3.16. SPI Interfaces

SC650T provides two SPI interfaces which only support master mode. The two interfaces are typically
applied for fingerprint identification.
Table 17: Pin Definition of SPI Interfaces
Pin Name Pin No
GPIO_22 58
GPIO_23 59
UART6_TXD 60
UART6_RXD 61
FP_SPI_CS0 203
FP_SPI_CS1 232
SC650T_Hardware_Design
I/O Description
Master clock signal of
DO
I2S interface
Clock signal of I2S
DO
interface
Channel selection signal
DO
of I2S interface
Data0 signal of I2S
IO
interface
Data1 signal of I2S
IO
interface
Data2 signal of I2S
IO
interface
Data3 signal of I2S
IO
interface
I/O Description
DO Chip selection signal of SPI interface
DO Clock signal of SPI interface
DO Master out slave in of SPI interface
DI Master in salve out of SPI interface
DO Chip selection signal of SPI interface
DO Chip selection signal of SPI interface
Smart LTE Module Series
SC650T Hardware Design
Comment
I2S_MCLK
I2S_1_SCK
I2S_1_WS
I2S_1_D0
I2S_1_D1
I2S_1_D2
I2S_1_D3
Comment
Can be multiplexed
into SPI_CS.
Can be multiplexed
into SPI_CLK.
Can be multiplexed
into SPI_MOSI.
Can be multiplexed
into SPI_MISO.
Used for fingerprint
identification by
default. Can be
60 / 131