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Quectel Manuals
Control Unit
Smart LTE Module Series
Hardware design
Quectel Smart LTE Module Series Hardware Design page 31
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TP0_I2C_
206
SDA
TP1_RST
136
TP1_INT
137
TP1_I2C_
204
SDA
TP1_I2C_
205
SCL
LCM Interfaces
Pin Name
Pin No.
LCD_BIAS_P
21
LCD_BIAS_N
22
WLED_EN
158
WLED_PWM
30
LCD0_RST
127
LCD0_TE
126
LCD1_RST
113
LCD1_TE
114
DSI0_CLK_N
116
DSI0_CLK_P
115
DSI0_LN0_N
118
DSI0_LN0_P
117
DSI0_LN1_N
120
SC650T_Hardware_Design
I2C data signal of
OD
touch panel (TP0)
Reset signal of
DO
touch panel (TP1)
Interrupt signal of
DI
touch panel (TP1)
I2C data signal of
OD
touch panel (TP1)
I2C clock signal of
OD
touch panel (TP1)
I/O
Description
LCD positive bias
PO
voltage.
LCD negative bias
AI
voltage.
LCD enable for
DO
backlight.
DO
PWM signal output
DO
LCD0 reset signal
LCD0 tearing effect
DI
signal
DO
LCD1 reset signal
LCD1 tearing effect
DI
signal
LCD0 MIPI clock
AO
signal (negative)
LCD0 MIPI clock
AO
signal (positive)
LCD0 MIPI lane 0
AO
data signal
(negative)
LCD0 MIPI lane 0
AO
data signal
(positive)
LCD0 MIPI lane 1
AO
data signal
(negative)
Smart LTE Module Series
SC650T Hardware Design
1.8V power domain.
V
max=0.45V
1.8V power domain.
OL
V
min=1.35V
Active low.
OH
V
max=0.63V
IL
1.8V power domain.
V
min=1.17V
IH
1.8V power domain.
1.8V power domain.
DC
Comment
Characteristics
V
max=0.45V
1.8V power domain.
OL
V
min=1.35V
Active low.
OH
V
max=0.63V
IL
1.8V power domain.
V
min=1.17V
IH
V
max=0.45V
1.8V power domain.
OL
V
min=1.35V
Active low.
OH
V
max=0.63V
IL
1.8V power domain.
V
min=1.17V
IH
30 / 131
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