Quectel Smart LTE Module Series Hardware Design page 33

Camera Interfaces
Pin Name Pin No.
CSI0_CLK_N 89
CSI0_CLK_P 88
CSI0_LN0_N 91
CSI0_LN0_P 90
CSI0_LN1_N 93
CSI0_LN1_P 92
CSI0_LN2_N 95
CSI0_LN2_P 94
CSI0_LN3_N 97
CSI0_LN3_P 96
CSI2_CLK_N 78
CSI2_CLK_P 77
CSI2_LN0_N 80
SC650T_Hardware_Design
I/O Description
MIPI clock signal of
AI rear camera
(negative)
MIPI clock signal of
AI rear camera
(positive)
MIPI lane 0 data
AI signal of rear
camera (negative)
MIPI lane 0 data
AI signal of rear
camera (positive)
MIPI lane 1 data
AI signal of rear
camera (negative)
MIPI lane 1 data
AI signal of rear
camera (positive)
MIPI lane 2 data
AI signal of rear
camera (negative)
MIPI lane 2 data
AI signal of rear
camera (positive)
MIPI lane 3 data
AI signal of rear
camera (negative)
MIPI lane 3 data
AI signal of rear
camera (positive)
MIPI clock signal of
AI front camera
(negative)
MIPI clock signal of
AI front camera
(positive)
MIPI lane 0 data
AI signal of front
camera (negative)
Smart LTE Module Series
SC650T Hardware Design
DC
Comment
Characteristics
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