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CSI2_LN0_P
79
CSI2_LN1_N
82
CSI2_LN1_P
81
CSI2_LN2_N
84
CSI2_LN2_P
83
CSI2_LN3_N
86
CSI2_LN3_P
85
MCAM_MCLK 99
SCAM_MCLK
100
MCAM_RST
74
MCAM_
73
PWDN
SCAM_RST
72
SCAM_
71
PWDN
CAM_I2C_
75
SCL
CAM_I2C_
76
SDA
DCAM_MCLK
194
CAM4_MCLK
236
DCAM_RST
180
SC650T_Hardware_Design
MIPI lane 0 data
AI
signal of front
camera (positive)
MIPI lane 1 data
AI
signal of front
camera (negative)
MIPI lane 1 data
AI
signal of front
camera (positive)
MIPI lane 2 data
AI
signal of front
camera (negative)
MIPI lane 2 data
AI
signal of front
camera (positive)
MIPI lane 3 data
AI
signal of front
camera (negative)
MIPI lane 3 data
AI
signal of front
camera (positive)
Master clock signal
DO
of rear camera
Master clock signal
DO
of front camera
Reset signal of rear
DO
camera
Power down signal
DO
of rear camera
Reset signal of front
DO
camera
Power down signal
DO
of front camera
I2C clock signal of
OD
camera
I2C data signal of
OD
camera
Master clock signal
DO
of depth camera
Master clock signal
DO
of fourth camera
DO
Reset
signal
Smart LTE Module Series
SC650T Hardware Design
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
of V
max=0.45V
OL
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
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